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公开(公告)号：US08340215B2
公开(公告)日：2012-12-25
申请号：US10206706
申请日：2002-07-26
CPC分类号： H04B1/001 , H04B1/0003 , H04B1/406
摘要： A radio communications device 100 including a processor 120 having a digital signal processor (DSP) coupled to a transceiver 110. The transceiver includes a digital-to-phase synthesizer having one or more independently variable frequency or phase signal outputs coupled to a transmitter and/or to a receiver. The variable frequency and phase outputs of the digital-to phase synthesizer are mixed with corresponding received signals and are capable of frequency or phase modulating information signals for transmission. Amplitude modulated signals may be provided through polar modulation by combining synthesizer outputs at a summer.
摘要翻译： 无线电通信设备100包括具有耦合到收发机110的数字信号处理器（DSP）的处理器120.收发器包括具有一个或多个独立可变频率或相位信号输出的数/模相位合成器，耦合到发射机和/ 或接收器。 数字到相位合成器的可变频率和相位输出与对应的接收信号混合，并能够进行频率或相位调制信息信号进行传输。 可以通过在夏天组合合成器输出通过极性调制来提供幅度调制信号。
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公开(公告)号：US20060098771A1
公开(公告)日：2006-05-11
申请号：US10983447
申请日：2004-11-08
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03K5/133 , H03K5/135 , H03K2005/00286 , H03L7/0812 , H04L7/0337
摘要： A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.
摘要翻译： DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头用于接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。
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3.发明申请System and method for providing an input to a distributed power amplifying system 有权用于向分布式功率放大系统提供输入的系统和方法公开(公告)号：US20060250189A1
公开(公告)日：2006-11-09
申请号：US11123309
申请日：2005-05-06
申请人： Bruce Thompson , Robert Stengel
发明人： Bruce Thompson , Robert Stengel
IPC分类号： H03F3/60
CPC分类号： H03F3/605
摘要： A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.
摘要翻译： 提供了一种用于向分布式功率放大系统提供输入的系统和方法。 在一个实施例中，分布式功率放大系统包括多个放大部分（102,104,106和108）和多个驱动器（110,112,114和116）。 多个驱动器中的每个驱动器接收公共发送信号（118）和单独的控制信号（120,122,124和126）。 所述多个驱动器中的每个驱动器独立地对所述公共发送信号进行预处理，以向所述多个放大部分中的每一个提供发送输出信号（128,130,132和134）。 提供给多个驱动器中的每一个的公共发送信号基于各个控制信号进行预处理。
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公开(公告)号：US06897687B2
公开(公告)日：2005-05-24
申请号：US10382696
申请日：2003-03-06
申请人： Nicholas Cafaro , Robert Stengel
发明人： Nicholas Cafaro , Robert Stengel
CPC分类号： H03C3/06
摘要： A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.
摘要翻译： 频率发生器（10）包括具有用于提供中间输出的累加器（18或28）的直接数字合成器（14）和用于内插中间输出的数字内插器（16），以提供具有降低的电磁干扰的输出信号。 数字内插器可以包括数/模转换器（22）或数字 - 时间转换器（32）中的至少一个转换器。 频率发生器还可以包括应用于直接数字合成器的输入端的数字可编程扩展功能（12）。
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5.发明授权公开(公告)号：US07143125B2
公开(公告)日：2006-11-28
申请号：US10414698
申请日：2003-04-16
IPC分类号： G06F1/02
CPC分类号： G06F1/025 , G06F2211/902
摘要： A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.
摘要翻译： 具有噪声整形电路的直接数字合成器（30）可以包括具有量化器（40）的无ROM直接数字合成器和包含量化器的噪声整形环路，用于对来自量化器的噪声造成的量化噪声进行整形。 噪声整形环路可以包括噪声整形滤波器（44），并且噪声整形环路可以将与量化器的输入信号（49）和来自量化器的输出信号（43）之间的差值反馈给噪声整形滤波器。 无ROM直接数字合成器还可以包括在量化器的输入处组合的抖动（39）。
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公开(公告)号：US06674329B1
公开(公告)日：2004-01-06
申请号：US10184504
申请日：2002-06-27
IPC分类号： H03F360
CPC分类号： H03F3/605
摘要： A distributed amplifier consistent with certain embodiments of the present invention has a plurality of amplifier sections 1 through N (302, 306) with each amplifier section having an input and an output. A plurality of N input transmission line sections are connected in series, with inputs of the 1 through N amplifier sections interconnected at their inputs along the series of input transmission line sections. A plurality of N output transmission line sections are also connected in series, with outputs of the 1 through N amplifier sections interconnected at their outputs along the series of input transmission line sections. A load (160) can be driven by an output at the Nth amplifier section (108). A high-pass filter (310) connects a dummy load (150) to the output of the first amplifier section (302). The input and output transmission line sections can, for example, be lumped element T sections and the high-pass filter can be made of a lumped element half section. To achieve the desired stability enhancement, the high pass filter section has a cutoff frequency equal to or greater than the cutoff frequency of the output transmission line sections. A similar high pass filter and dummy load can be used in the input transmission line network.
摘要翻译： 与本发明的某些实施例一致的分布式放大器具有多个放大器部分1至N（302,306），每个放大器部分具有输入和输出。 多个N个输入传输线段被串联连接，1到N个放大器部分的输入在它们的输入端沿着一系列输入传输线部分互连。 多个N个输出传输线段也被串联连接，其中1至N个放大器部分的输出沿其一系列输入传输线部分在其输出处互连。 负载（160）可以由第N放大器部分（108）的输出驱动。 高通滤波器（310）将虚拟负载（150）连接到第一放大器部分（302）的输出端。 输入和输出传输线部分可以例如是集总元件T部分，并且高通滤波器可以由集总元件半部分制成。 为了实现期望的稳定性增强，高通滤波器部分具有等于或大于输出传输线部分的截止频率的截止频率。 在输入传输线网络中可以使用类似的高通滤波器和虚拟负载。
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公开(公告)号：US20070111679A1
公开(公告)日：2007-05-17
申请号：US11280626
申请日：2005-11-16
申请人： Bruce Thompson , Leng Ooi , Robert Stengel
发明人： Bruce Thompson , Leng Ooi , Robert Stengel
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.
摘要翻译： 矢量信号处理器（80）可以包括数字到时间转换器（DTC），RF存储器（RFM）或电子可调谐传输线（ETTL）（82），混频器或其它移相器（70） DTC或ETTL的输出，以及用于选择性地控制DTC，RFM或ETTL的谐波处理的控制器以及混频器的相位处理。 矢量信号处理器可以分离基本信号相对于基波信号的谐波的相对相位。 矢量信号处理器使用基本信号和相关谐波分量的选择性相位处理。 在具体实施例中，矢量信号处理器消除基波信号的谐波，更具体地可以消除基波信号的三次谐波。
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公开(公告)号：US20050168260A1
公开(公告)日：2005-08-04
申请号：US10767088
申请日：2004-01-29
申请人： Andrew Tomerlin , Robert Stengel
发明人： Andrew Tomerlin , Robert Stengel
CPC分类号： H03L7/0802 , H03K5/133 , H03K2005/00019 , H03L7/0812 , H03L7/0814 , H03L7/16
摘要： A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, . . . , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
摘要翻译： 与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并且具有N个延迟元件（12,14,16,18 ... 20） 提供多个N个延迟输出（T（0）至T（N））。 可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。 可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。 可配置处理阵列具有可配置电路元件（104,130,150）的阵列。 可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。
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公开(公告)号：US20050063455A1
公开(公告)日：2005-03-24
申请号：US10964114
申请日：2004-10-13
申请人： Andrew Tomerlin , Nicholas Cafaro , Robert Stengel
发明人： Andrew Tomerlin , Nicholas Cafaro , Robert Stengel
IPC分类号： H04B1/707
CPC分类号： H04B1/707
摘要： A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
摘要翻译： 与本发明的某些实施例一致的电路具有N个参考时钟频率（230）的源，其中N是大于1的整数。 N个扩展器电路（954）接收N个参考时钟频率并从其产生N个频率扩展的输出时钟信号。 多个N种子花式（958）产生N个种子更新值。 多个N个种子寄存器（962）各自接收N个种子更新值中的一个并从其生成N个种子掩码。 多个N个逻辑电路（966）分别接收N个种子掩码和N个频率扩展输出时钟信号之一。 N个逻辑电路（966）中的每一个从种子掩码和频率扩展输出时钟信号产生伪随机序列。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。
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公开(公告)号：US06667659B2
公开(公告)日：2003-12-23
申请号：US10085544
申请日：2002-02-28
申请人： Robert Stengel , Bruce Thompson
发明人： Robert Stengel , Bruce Thompson
IPC分类号： H03F360
CPC分类号： H03F3/607 , H03F1/0277
摘要： A distributed amplifier arrangement (300) is provided in which a plurality of input signals (S1(t), . . . SN(t)) are separately controlled by a drive generator circuit (315) to produce modulation of a virtual load impedance at each amplifier stage. This permits each stage (302, 304, . . . 310) of the distributed amplifier (300) to operate at maximum efficiency by permitting the stage to produce an output voltage that approaches the supply voltage. As the output power is reduced, efficiency is maintained by systematically reducing the number of stages contributing to the output to the load.
摘要翻译： 提供分布式放大器装置（300），其中多个输入信号（S1（t），...，SN（t））由驱动发生器电路（315）分别控制，以产生虚拟负载阻抗的调制 每个放大器级。 这允许分布式放大器（300）的每个级（302,304，...）通过允许级产生接近电源电压的输出电压以最大的效率工作。 随着输出功率的降低，通过系统地减少有助于输出到负载的级数来维持效率。
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