公开(公告)号：US07249223B2

公开(公告)日：2007-07-24

申请号：US10916298

申请日：2004-08-11

申请人： William C. Moyer ,  Craig D. Shaw

发明人： William C. Moyer ,  Craig D. Shaw

IPC分类号： G06F12/00

CPC分类号： G06F12/0215

摘要： A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an address is driven onto the bus (12). Before the address is qualified, data corresponding to the address is prefetched. Prefetching the data before the address is qualified allows prefetches to be accomplished sooner.

摘要翻译： 提供了一种用于在数据处理系统（10）中预取的方法和装置。 数据处理系统（10）具有总线主机（14）和耦合到总线（12）的存储器控​​制器（16）。 存储器（18）耦合到存储器控制器（16）。 在数据处理系统（14）中，地址被驱动到总线（12）上。 在地址合格之前，与地址对应的数据将被预取。 在地址合格之前预取数据可以提前完成预取。

公开(公告)号：US07434264B2

公开(公告)日：2008-10-07

申请号：US10384024

申请日：2003-03-07

申请人： William C. Moyer ,  Joseph C. Circello ,  Craig D. Shaw

发明人： William C. Moyer ,  Joseph C. Circello ,  Craig D. Shaw

IPC分类号： H04L9/32 ,  G06G7/04 ,  G06F3/00

CPC分类号： G06F21/85 ,  G06F2221/2113 ,  G06F2221/2141

摘要： A flexible peripheral access protection mechanism within a data processing system (10, 100). In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for particular bus access types (e.g. read and write accesses). Also, in one embodiment, each peripheral (22, 24) within the data processing system (10) includes a corresponding trust attribute (80, 84), write protect indicator (81, 85), and a privilege protect indicator (82, 86). Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access). Also, through the use of the privilege level modifiers, a the bus master can be forced to a particular privilege level for a particular bus access.

摘要翻译： 一种在数据处理系统（10,100）内的灵活的外围设备访问保护机制。 在一个实施例中，数据处理系统（10）内的每个主机（14,15）包括用于特定总线访问类型的对应的权限级别修改器（70,74）和对应的信任属性（71,72,75,76）（例如， 读写访问）。 此外，在一个实施例中，数据处理系统（10）内的每个外围设备（22,24）包括相应的信任属性（80,84），写入保护指示符（81,85）和特权保护指示符（82,86 ）。 因此，在一个实施例中，当总线主机具有适当的特权级别和外设所需的适当的信任级别（并且外围设备不被写保护时，如果总线访问是 写访问）。 此外，通过使用特权级别修改器，可以将总线主机强制为特定总线访问的特定权限级别。

公开(公告)号：US10031773B2

公开(公告)日：2018-07-24

申请号：US14185005

申请日：2014-02-20

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F9/48

摘要： Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

公开(公告)号：US09372723B2

公开(公告)日：2016-06-21

申请号：US14231784

申请日：2014-04-01

申请人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

发明人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

IPC分类号： G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/48

摘要： A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.

摘要翻译： 数据处理系统包括处理器核心和订购范围管理器电路。 处理器核心向当前订购范围发送当前由处理器核心执行的任务的第一订购范围标识符和用于任务的下一个订购范围的第二订购范围标识符的指示。 订购范围管理器从处理器核心接收第一和第二订购范围标识符的指示，并且响应于确定第一任务是第一个转换顺序任务，向处理器核心提供无任务切换指示符 第一个订购范围标识符，该处理器核心被授权执行下一个订购范围。 处理器核心从当前订购范围内的执行转变为按顺序排序范围执行，而不响应于提供无任务切换指示器而执行任务切换。

公开(公告)号：US20160098313A1

公开(公告)日：2016-04-07

申请号：US14504702

申请日：2014-10-02

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/07 ,  G06F9/50

CPC分类号： G06F11/0757 ,  G06F11/0724

摘要： Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred.

摘要翻译： 分配给核心的每个任务可以被认为是一个“主动”任务。 看门狗信号的顺序选通信号可以在时间上间隔一段持续时间。 选通信号之间的持续时间长于活动任务的预期持续时间。 通过知道所有被监视的任务预期在预期的时间内执行，选通信号之间的持续时间可以被设置为比预期的时间长。 如果任务没有被下一个选通转换为非活动状态，则发生看门狗错误。

公开(公告)号：US09268527B2

公开(公告)日：2016-02-23

申请号：US13841630

申请日：2013-03-15

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F7/483 ,  G06F7/499

CPC分类号： G06F7/483 ,  G06F7/49905

摘要： A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant.

摘要翻译： 浮点值可以表示数字或不是数字（NaN）的数据。 具有存储信息的数据字段的NaN的浮点值，例如表示通过指令传播NaN值的次数的传播计数。 NaN评估指令可以确定一个或多个操作数是否是特定类型的NaN操作数，如果可以生成作为不同类型的NaN的结果。 可以基于作为结果提供的不同类型的NaN产生异常。

公开(公告)号：US20150277973A1

公开(公告)日：2015-10-01

申请号：US14231789

申请日：2014-04-01

申请人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

发明人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

IPC分类号： G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/48

摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

摘要翻译： 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 硬件模块在订购范围管理器的第一存储位置处存储第一订购范围标识符。 第一个订购范围标识符指示第一个任务正在操作的第一个订购范围。订购范围管理器增加第一个订购范围标识符以创建新的订购范围标识符。 响应于确定处理器核被授权将第一任务从第一排序范围转换到与新排序范围标识符相关联的第二排序范围，订购范围管理器向处理器核提供提示信息。 处理器核心从第一订购范围转换到第二订购范围，而不响应于提示信息完成任务切换。

公开(公告)号：US09104403B2

公开(公告)日：2015-08-11

申请号：US12858599

申请日：2010-08-18

申请人： Gary R. Morrison ,  William C. Moyer

发明人： Gary R. Morrison ,  William C. Moyer

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F11/14 ,  G06F11/16

CPC分类号： G06F9/30145 ,  G06F11/1405 ,  G06F11/1479 ,  G06F11/1497 ,  G06F11/1629

摘要： A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

摘要翻译： 一种方法包括：第一次解码指令以获得第一解码指令; 第二次对指令进行解码以获得第二解码指令; 将所述第一解码指令的至少一部分与所述第二解码指令的至少一部分进行比较; 并且当所述第一解码指令的至少一部分与所述第二解码指令的所述至少一部分匹配时，执行所述指令。

公开(公告)号：US08739165B2

公开(公告)日：2014-05-27

申请号：US12017988

申请日：2008-01-22

申请人： Andrew C. Russell ,  William C. Moyer

发明人： Andrew C. Russell ,  William C. Moyer

IPC分类号： G06F9/46

CPC分类号： G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

摘要： Threads may be scheduled to be executed by one or more cores depending upon whether it is more desirable to minimize power or to maximize performance. If minimum power is desired, threads may be schedule so that the active devices are most shared; this will minimize the number of active devices at the expense of performance. On the other hand, if maximum performance is desired, threads may be scheduled so that active devices are least shared. As a result, threads will have more active devices to themselves, resulting in greater performance at the expense of additional power consumption. Thread affinity with a core may also be taken into consideration when scheduling threads in order to improve the power consumption and/or performance of an apparatus.

摘要翻译： 线程可以被调度为由一个或多个核执行，这取决于是否更希望最小化功率或最大化性能。 如果需要最小功率，则可以调度线程，使得有效设备是最共享的; 这将以牺牲性能为代价来最小化活动设备的数量。 另一方面，如果需要最大性能，则可以调度线程，使得有源设备最不共享。 因此，线程将自己拥有更多的活动设备，导致更高的性能，而牺牲额外的功耗。 为了提高设备的功耗和/或性能，调度线程时也可以考虑与核心的线程亲和度。

公开(公告)号：US08725975B2

公开(公告)日：2014-05-13

申请号：US11619294

申请日：2007-01-03

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1008

摘要： A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.

摘要翻译： 一种方法包括初始化硬件计数器的计数器值。 该方法还包括迭代地调整计数器值，并且使用基于计数器值的存储器地址将初始化值存储到存储器位置。 该方法还包括基于通过迭代调整和存储同时计算值与等待点值的比较来产生中断请求。 存储器件包括存储器阵列和初始化模块。 初始化模块包括计数器，用于存储等待点值的寄存器，被配置为将初始化值写入与基于计数器的计数器值的存储器地址相关联的存储器阵列的存储器位置的写入逻辑，以及中断逻辑 被配置为基于计数器的计数器值与等待点值的比较来生成中断请求。