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公开(公告)号：US4782249A
公开(公告)日：1988-11-01
申请号：US81076
申请日：1987-08-03
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.
摘要翻译： CMOS可编程逻辑阵列包括接收用于形成第二组逻辑小区的第一组输入逻辑信号的逻辑“与”面和接收用于形成第三组输出逻辑信号的逻辑最小值的逻辑“或”平面。 每种类型的逻辑平面包含多个逻辑门。 每个平面类型可以通过向每个输入添加一个逻辑反相器并输出该另一个平面类型而形成。 互连确定用于定义每个平面的每个逻辑门的输出处的信号的逻辑方程的输入信号的组合。 静态锁存器用于保持输入和最小逻辑信号的状态。 逻辑平面和锁存器可以响应于两相时钟信号而被操作。
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公开(公告)号：US5345939A
公开(公告)日：1994-09-13
申请号：US157760
申请日：1993-11-24
CPC分类号： G10K11/348 , G01B17/06 , G01S15/8918 , G01S7/52047
摘要： A PASS ultrasonic system includes a separate receive channel for each respective element in an ultrasonic transducer array which imparts a delay to the echo signal produced by each respective element. The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam which can be readily interpreted even when the transmit beam does not emanate from the center of the array.
摘要翻译： PASS超声波系统包括用于超声换能器阵列中的每个相应元件的单独的接收通道，其对由每个相应元件产生的回波信号施加延迟。 延迟的回波信号被相加以形成转向的动态聚焦和动态窗口的接收波束，即使当发射波束不从阵列的中心发射时，其也可以容易地解释。
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公开(公告)号：US5111695A
公开(公告)日：1992-05-12
申请号：US551093
申请日：1990-07-11
CPC分类号： G10K11/346 , G01S7/52046
摘要： A method for dynamic focus of received energy, in a vibratory energy imaging system, into a beam in which contribution from transducers in an array of N such transducers, are progressively enabled to contribute to beam focussing dependent upon distance between a particular j-th transducer (where 1.ltoreq.j.ltoreq.N) is responsive to the depth, or range R, of the focal point at any instant of time; the initial steering angle .theta., with respect to the array normal, is used in conjunction with a range clock, to determine the time when each off-normal transducer channel is enabled to add to the beam (dynamic apodization) and to finely adjust the channel time delay to properly focus the beam after the enablement of the channel.
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4.发明授权Apparatus for implementation of desired input/output function in an electronic system having a plurality of channels 失效用于在具有多个通道的电子系统中实现期望的输入/输出功能的装置
公开(公告)号：US5047771A
公开(公告)日：1991-09-10
申请号：US518600
申请日：1990-05-03
CPC分类号： G06F1/03 , H03M1/1042 , H03M1/1235
摘要： Apparatus for providing a desired output signal as a function of a single-valued input signal in an electronic system, includes: an addressable memory, having a plurality L locations, each for storage of a data word of B bits; a circuit for storing in each of the L locations of the memory means a B-bit data word having a value selected to provide a particular output value; and circuitry for converting a present single-valued increment of input signal to a unique address, within the range of allowable locations of the memory, to cause each increment of input signal to select the associated one of the L data word locations, from which to output corresponding data.
摘要翻译： 用于在电子系统中提供作为单值输入信号的函数的期望输出信号的装置包括：具有多个L个位置的可寻址存储器，每个位置用于存储B位数据字; 用于在存储器装置的每个L位置存储具有被选择以提供特定输出值的值的B位数据字的电路; 以及用于在存储器的可允许位置的范围内将输入信号的当前单值增量转换为唯一地址的电路，以使输入信号的每个增量选择所述L个数据字位置中的相关联的一个， 输出相应的数据。
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5.发明授权Apparatus for testing data conversion/transfer functions in a vibratory energy imaging system 失效用于在振动能量成像系统中测试数据转换/传递功能的装置
公开(公告)号：US5047770A
公开(公告)日：1991-09-10
申请号：US518595
申请日：1990-05-03
摘要： Apparatus for testing data conversion/transfer functions in each of a plurality N of channels of a vibratory energy imaging system includes a multiplexer for providing, to an addressable memory having a plurality of L=2.sup.M locations in each of which a data word of B bits can be stored, a selected one of an input data word and a test data word, each of which can address one of the L locations of the memory means. The address multiplexer facilitates retrieval from memory of a B-bit data word having a value selected to implement a selected function for that channel, so that comparision of data from the selected test address with the data which has been sent to that location for storage, will indicate if proper data is stored for carrying out the designated function.
摘要翻译： 用于测试振动能量成像系统的多个N个通道中的每一个中的数据转换/传递功能的装置包括多路复用器，用于向具有多个L = 2M位置的可寻址存储器提供B位的数据字 可以存储输入数据字和测试数据字中的所选择的一个，每个可以寻址存储器装置的L个位置之一。 地址复用器便于从具有被选择为实现该信道的所选功能的值的B位数据字的存储器中检索，以便将来自所选测试地址的数据与已发送到该位置的数据进行比较以进行存储， 将指示是否存储正确的数据以执行指定的功能。
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6.发明授权Methods of correcting data conversion/transfer errors in a vibratory energy imaging system utilizing a plurality of channels 失效在利用多个通道的振动能量成像系统中校正数据转换/传送错误的方法
公开(公告)号：US5047769A
公开(公告)日：1991-09-10
申请号：US518596
申请日：1990-05-03
CPC分类号： H03M1/1042 , H03M1/1235
摘要： A method for correcting data conversion/transfer errors in each of a plurality N of channels of a vibratory energy imaging system, by: providing an addressable memory having a plurality L=2.sup.M locations, each for storage of a data word of B bits; then storing in each of the L locations of the memory means a B-bit data word having a value selected to cause the output-to-input transfer function for that channel to assume a desired relationship, with respect to a standard transfer measure; and selecting that one of the L data word locations, responsive to that actual one of an M-bit data word output from a channel ADC or from a data bus, responsive to a test signal, in which to place corresponding data.
摘要翻译： 一种用于通过以下方式来校正振动能量成像系统的多个N个通道中的每一个中的数据转换/传送错误的方法：提供具有多个L = 2M个位置的可寻址存储器，每个用于存储B位数据字; 然后在存储器装置的每个L位置存储一个B位数据字，该B位数据字被选择为使得该通道的输出到输入传递函数相对于标准传送测量呈现期望的关系; 以及响应于来自信道ADC或从数据总线输出的M位数据字中的实际的一个，响应于在其中放置相应数据的测试信号，选择L个数据字位置中的一个。
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公开(公告)号：US4983970A
公开(公告)日：1991-01-08
申请号：US500164
申请日：1990-03-28
CPC分类号： G01S7/52046 , G10K11/346
摘要： A method for generating a stream of digital data words, each representing an analog signal amplitude from a beam of vibratory energy received by a plurality N of transducers each associated with one of a like number of separate channels of a phased array, uses the steps of: sampling, after a delay of a multiple number of cycles at a fixed frequency F, an analog input signal in each channel at a fixed frequency F for conversion to a digital data word at each sample; then demodulating the digital data word stream in each channel to baseband and reducing the data word rate by a factor D; and phase-rotating the baseband data stream of each channel by a phase difference .DELTA..phi. determined by the focal range R and steering angle .theta. to obtain, along both the sampling delay, a different channel time delay t.sub.d,j, for each j-th channel, where 1.ltoreq.j.ltoreq.N, necessary to steer and focus the beam to a desired angle/range combination. Apparatus for generating the stream of digital data words is disclosed, and uses a special output-switching section in each channel to allow a pipelined coherent summation to be obtained across the entire phased transducer array.
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8.发明授权Method of generating, in the analog regime, weighted summations of digital signals 失效在模拟方式中产生数字信号的加权求和的方法
公开(公告)号：US5151970A
公开(公告)日：1992-09-29
申请号：US722801
申请日：1991-06-28
申请人： William E. Engeler
发明人： William E. Engeler
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： A method is disclosed for operating electronic apparatus for generating a weighted summation of digital input signals as manifested in electric signal form, each sample of which digital input signals has a plurality B in number of bits identified by respective ones of consecutive ordinal numbers first through B.sup.th assigned in order of decreasing significance. Successive samples of each of the digital input signals is supplied in a respective stream, such that the respective streams of samples are parallel in time with each other. Each B-bit sample of said digital input signals is recoded into a plurality D in number of binary-coded digits, as manifested in electric signal form and as identified by consecutive ordinal numbers frist through D.sup.th assigned in order of decreasing significance of the respective weighting assigned each of the D binary-coded digits, B and D begin respectively a relatively larger positive integer and a relatively smaller positive integer. Each set of temporally aligned digits is converted to a set of corresponding analog electric signals, consisting of D subsets each containing analog electric signals corresponding to digits of the same assigned weighting. A weighted summation procedure is performed on the streams of partial weighted summation results, thereby to obtain a stream of final weighted summation results as manifested in electric signal form.
摘要翻译： 公开了一种用于操作电子装置的方法，用于产生数字输入信号的加权求和，其表现为电信号形式，其中每个样本的数字输入信号具有多个B，其数目由连续序数第一至第B 按照意义递减的顺序分配。 每个数字输入信号的连续样本在相应流中提供，使得相应的样本流在时间上彼此平行。 所述数字输入信号的每个B位采样被以多个二进制编码的数字重新编码为多个D，如电信号形式所示，并且由通过Dth分配的连续序数确定的顺序是按照相应加权的显着性降低的顺序 分配了每个D二进制编码数字，B和D分别开始相对较大的正整数和相对较小的正整数。 每组时间对齐的数字被转换成一组相应的模拟电信号，由一组D子集组成，每个子集包含对应于相同分配权重的数字的模拟电信号。 对部分加权求和结果的流执行加权求和程序，从而获得表示为电信号形式的最终加权求和结果流。
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9.发明授权
公开(公告)号：US4937775A
公开(公告)日：1990-06-26
申请号：US274473
申请日：1988-11-21
CPC分类号： G06F17/15
摘要： Apparatus for the cross-correlation of two complex sampled digital data signals X and Y uses a first N-stage CORDIC rotator of pipeline sequential form for rotating each of the real and imaginary data portions of the first (X) complex sampled signal sequentially through a summation of angles .theta.=.xi..sub.i .alpha..sub.i where .xi..sub.i =+1 or -1, .alpha..sub.1 =90.degree. and .alpha..sub.n-2 =tan.sup.-1 (2.sup.-n) for n=0, 1, 2, 3, . . . N-2) until X.sub.Im is approximately zero and a substantially zero phase angle is reached. The sign from each i-th stage, of this first pipeline is also utilized to determine the sign of rotation in each like-positioned i-th stage of a plurality M of additional CORDIC pipeline rotators, where M is the total number of time delays at which the cross-correlation function is evaluated. The real and imaginary portions of the complete M-th interval cross-correlation product are each obtained by multiplying the associated complex output of each of the Y pipeline rotators by the first pipeline magnitude signal output; N samples are then summed to provide at the j-th rotator output the appropriate pair of the real and imaginary parts of the j-th complex digital data output sample C(j).
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10.发明授权Architecture for high sampling rate, high resolution analog-to-digital converter system 失效高采样率，高分辨率模数转换器系统的架构
公开(公告)号：US4903026A
公开(公告)日：1990-02-20
申请号：US274082
申请日：1988-11-22
CPC分类号： H03M1/1042 , H03M1/168
摘要： A high resolution analog-to-digital (A/D) converter (14) and a pipelined A/D converter are used in a single system so that unknown offset and gain errors of the pipe-lined A/D converter are determined and corrected. Each stage of the pipelined A/D converter includes a flash A/D converter (16), a corresponding digital-to-analog (D/A) converter (18), and a differential amplifier (20) so that, in each stage the output voltage of the D/A converter is subtracted from a sample of the analog input voltage, to constitute the input signal for the next stage. The flash A/D converter of each stage addresses digital words in memory (22) which, when summed by an adder chain (24), constitute the output signal of the system. The flash A/D converter output signals are also supplied to corresponding stages of a shift register (28 or 28') which accumulates the memory address bits. A comparator and finite state machine (26) receives the memory address bits from the shift register and iteratively compares the digital output signals of the pipelined A/D converter and the high resolution A/D converter and corrects the words in memory addressed by the flash A/D converters to improve resolution of the system.
摘要翻译： 在单个系统中使用高分辨率模数（A / D）转换器（A / D）转换器（14）和流水线A / D转换器，以便确定和校正管道内A / D转换器的未知偏移和增益误差 。 流水线A / D转换器的每个级包括闪存A / D转换器（16），对应的数模（D / A）转换器（18）和差分放大器（20），使得在每个级 从模拟输入电压的样本中减去D / A转换器的输出电压，构成下一级的输入信号。 每级的闪存A / D转换器解决存储器（22）中的数字字，当加法器链（24）相加时，它构成系统的输出信号。 闪存A / D转换器输出信号也提供给积累存储器地址位的移位寄存器（28或28'）的相应级。 比较器和有限状态机（26）从移位寄存器接收存储器地址位，并且迭代地比较流水线A / D转换器和高分辨率A / D转换器的数字输出信号，并校正由闪存寻址的存储器中的字 A / D转换器提高系统的分辨率。
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