公开(公告)号：US4937775A

公开(公告)日：1990-06-26

申请号：US274473

申请日：1988-11-21

申请人： William E. Engeler ,  Matthew N O'Donnell

发明人： William E. Engeler ,  Matthew N O'Donnell

IPC分类号： G06F17/16 ,  G06F17/15

CPC分类号： G06F17/15

摘要： Apparatus for the cross-correlation of two complex sampled digital data signals X and Y uses a first N-stage CORDIC rotator of pipeline sequential form for rotating each of the real and imaginary data portions of the first (X) complex sampled signal sequentially through a summation of angles .theta.=.xi..sub.i .alpha..sub.i where .xi..sub.i =+1 or -1, .alpha..sub.1 =90.degree. and .alpha..sub.n-2 =tan.sup.-1 (2.sup.-n) for n=0, 1, 2, 3, . . . N-2) until X.sub.Im is approximately zero and a substantially zero phase angle is reached. The sign from each i-th stage, of this first pipeline is also utilized to determine the sign of rotation in each like-positioned i-th stage of a plurality M of additional CORDIC pipeline rotators, where M is the total number of time delays at which the cross-correlation function is evaluated. The real and imaginary portions of the complete M-th interval cross-correlation product are each obtained by multiplying the associated complex output of each of the Y pipeline rotators by the first pipeline magnitude signal output; N samples are then summed to provide at the j-th rotator output the appropriate pair of the real and imaginary parts of the j-th complex digital data output sample C(j).

公开(公告)号：US5151970A

公开(公告)日：1992-09-29

申请号：US722801

申请日：1991-06-28

申请人： William E. Engeler

发明人： William E. Engeler

IPC分类号： G06N3/04

CPC分类号： G06N3/04

摘要： A method is disclosed for operating electronic apparatus for generating a weighted summation of digital input signals as manifested in electric signal form, each sample of which digital input signals has a plurality B in number of bits identified by respective ones of consecutive ordinal numbers first through B.sup.th assigned in order of decreasing significance. Successive samples of each of the digital input signals is supplied in a respective stream, such that the respective streams of samples are parallel in time with each other. Each B-bit sample of said digital input signals is recoded into a plurality D in number of binary-coded digits, as manifested in electric signal form and as identified by consecutive ordinal numbers frist through D.sup.th assigned in order of decreasing significance of the respective weighting assigned each of the D binary-coded digits, B and D begin respectively a relatively larger positive integer and a relatively smaller positive integer. Each set of temporally aligned digits is converted to a set of corresponding analog electric signals, consisting of D subsets each containing analog electric signals corresponding to digits of the same assigned weighting. A weighted summation procedure is performed on the streams of partial weighted summation results, thereby to obtain a stream of final weighted summation results as manifested in electric signal form.

摘要翻译： 公开了一种用于操作电子装置的方法，用于产生数字输入信号的加权求和，其表现为电信号形式，其中每个样本的数字输入信号具有多个B，其数目由连续序数第一至第B 按照意义递减的顺序分配。 每个数字输入信号的连续样本在相应流中提供，使得相应的样本流在时间上彼此平行。 所述数字输入信号的每个B位采样被以多个二进制编码的数字重新编码为多个D，如电信号形式所示，并且由通过Dth分配的连续序数确定的顺序是按照相应加权的显着性降低的顺序 分配了每个D二进制编码数字，B和D分别开始相对较大的正整数和相对较小的正整数。 每组时间对齐的数字被转换成一组相应的模拟电信号，由一组D子集组成，每个子集包含对应于相同分配权重的数字的模拟电信号。 对部分加权求和结果的流执行加权求和程序，从而获得表示为电信号形式的最终加权求和结果流。

公开(公告)号：US4903026A

公开(公告)日：1990-02-20

申请号：US274082

申请日：1988-11-22

申请人： Jerome J. Tiemann ,  William E. Engeler ,  Kenneth B. Welles

发明人： Jerome J. Tiemann ,  William E. Engeler ,  Kenneth B. Welles

IPC分类号： H03M1/10 ,  H03M1/16

CPC分类号： H03M1/1042 ,  H03M1/168

摘要： A high resolution analog-to-digital (A/D) converter (14) and a pipelined A/D converter are used in a single system so that unknown offset and gain errors of the pipe-lined A/D converter are determined and corrected. Each stage of the pipelined A/D converter includes a flash A/D converter (16), a corresponding digital-to-analog (D/A) converter (18), and a differential amplifier (20) so that, in each stage the output voltage of the D/A converter is subtracted from a sample of the analog input voltage, to constitute the input signal for the next stage. The flash A/D converter of each stage addresses digital words in memory (22) which, when summed by an adder chain (24), constitute the output signal of the system. The flash A/D converter output signals are also supplied to corresponding stages of a shift register (28 or 28') which accumulates the memory address bits. A comparator and finite state machine (26) receives the memory address bits from the shift register and iteratively compares the digital output signals of the pipelined A/D converter and the high resolution A/D converter and corrects the words in memory addressed by the flash A/D converters to improve resolution of the system.

摘要翻译： 在单个系统中使用高分辨率模数（A / D）转换器（A / D）转换器（14）和流水线A / D转换器，以便确定和校正管道内A / D转换器的未知偏移和增益误差 。 流水线A / D转换器的每个级包括闪存A / D转换器（16），对应的数模（D / A）转换器（18）和差分放大器（20），使得在每个级 从模拟输入电压的样本中减去D / A转换器的输出电压，构成下一级的输入信号。 每级的闪存A / D转换器解决存储器（22）中的数字字，当加法器链（24）相加时，它构成系统的输出信号。 闪存A / D转换器输出信号也提供给积累存储器地址位的移位寄存器（28或28'）的相应级。 比较器和有限状态机（26）从移位寄存器接收存储器地址位，并且迭代地比较流水线A / D转换器和高分辨率A / D转换器的数字输出信号，并校正由闪存寻址的存储器中的字 A / D转换器提高系统的分辨率。

公开(公告)号：US4839652A

公开(公告)日：1989-06-13

申请号：US56177

申请日：1987-06-01

申请人： Matthew O'Donnell ,  William E. Engeler ,  Thomas L. Vogelsong ,  Steven G. Karr ,  Sharbel E. Noujaim

发明人： Matthew O'Donnell ,  William E. Engeler ,  Thomas L. Vogelsong ,  Steven G. Karr ,  Sharbel E. Noujaim

IPC分类号： G06F3/05 ,  A61B8/00 ,  G01S7/52 ,  G01S7/523 ,  G01S15/89 ,  G10K11/34 ,  H03H17/00 ,  H03H17/06

CPC分类号： H03H17/0664 ,  G01S15/8918 ,  G01S7/52034 ,  G01S7/52046 ,  G10K11/346 ,  H03H2218/04

摘要： A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

公开(公告)号：US4240089A

公开(公告)日：1980-12-16

申请号：US952413

申请日：1978-10-18

申请人： William E. Engeler

发明人： William E. Engeler

IPC分类号： G11C19/28 ,  H01L29/768 ,  H01L29/94 ,  H01L29/78

CPC分类号： H01L29/94 ,  G11C19/282 ,  H01L29/76816 ,  H01L29/76866

摘要： In surface charge transfer devices a surface adjacent semiconductor layer of high resistivity and an underlying semiconductor layer of substantially lower resistivity are provided. The devices are operated to maintain depletion in the surface adjacent layer at least to the interface between the two layers to maintain substantially constant depletion depth and thereby provide substantially linear response.

摘要翻译： 在表面电荷转移装置中，提供具有高电阻率的表面相邻半导体层和基本上较低电阻率的下面的半导体层。 这些装置被操作以至少保持两层之间的界面处的表面相邻层的耗尽，以维持基本上不变的耗尽深度，从而提供基本上线性的响应。

公开(公告)号：US4178519A

公开(公告)日：1979-12-11

申请号：US934011

申请日：1978-08-16

申请人： William E. Engeler ,  Richard D. Baertsch

发明人： William E. Engeler ,  Richard D. Baertsch

IPC分类号： G11C19/28 ,  G11C27/04 ,  H01L29/768 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/76808 ,  G11C19/285 ,  G11C27/04

摘要： Input structures are described for sampling an analog signal and providing charge samples in accordance therewith to charge transfer devices.

摘要翻译： 描述了用于对模拟信号进行采样并根据其提供电荷样本的电荷转移装置的输入结构。

公开(公告)号：US5568446A

公开(公告)日：1996-10-22

申请号：US516078

申请日：1995-08-17

申请人： William E. Engeler ,  David B. Ribner

发明人： William E. Engeler ,  David B. Ribner

IPC分类号： G01S7/52 ,  G01S15/89 ,  G03B42/06 ,  A61B8/00

CPC分类号： G01S15/8979 ,  G01S7/52028 ,  G01S7/52033

摘要： A dual mode ultrasonic imager system operative in both a two dimensional 2-D) mode and doppler mode, includes a plurality of transducers for receiving analog ultrasonic signals and converting them to analog electrical signals, and an analog to digital (A/D) converter system for converting the analog electrical signals to digital signals for further processing. The A/D converter system includes a digital to analog (D/A) converter for converting the digital signals into analog feedback signals, and an analog summer for receiving the analog electrical signals and combining them with the analog feedback signals. An integrator is selectively coupled to receive an output signal from the analog summer and to generate an integrated analog signal. An A/D converter selectively receives, and converts to an equivalent digital signal, one of the integrated analog signal and an output signal of the analog summer. During the 2-D mode, the integrator is bypassed and the A/D converter receives the output signal of the analog summer for conversion to a digital signal. In the doppler mode, the A/D converter receives from the integrator the integrated analog signal and converts it to a digital signal.

摘要翻译： 一种双模超声波成像器系统，其工作于二维二维模式和多普勒模式，包括多个用于接收模拟超声波信号并将其转换为模拟电信号的换能器，以及模数（A / D）转换器 用于将模拟电信号转换为数字信号的系统用于进一步处理。 A / D转换器系统包括用于将数字信号转换为模拟反馈信号的数模（D / A）转换器，以及用于接收模拟电信号并将其与模拟反馈信号组合的模拟加法器。 积分器被选择性地耦合以接收来自模拟加法器的输出信号并产生积分的模拟信号。 A / D转换器选择性地接收并转换成等效数字信号，其中一个集成模拟信号和模拟夏天的输出信号。 在2-D模式下，积分器被旁路，A / D转换器接收模拟加法器的输出信号以转换为数字信号。 在多普勒模式下，A / D转换器从积分器接收积分的模拟信号并将其转换为数字信号。

公开(公告)号：US5345939A

公开(公告)日：1994-09-13

申请号：US157760

申请日：1993-11-24

申请人： William E. Engeler ,  Christopher M. W. Daft ,  John T. Pedicone ,  Theodore L. Rhyne

发明人： William E. Engeler ,  Christopher M. W. Daft ,  John T. Pedicone ,  Theodore L. Rhyne

IPC分类号： G01B17/06 ,  G01S7/52 ,  G01S15/89 ,  G10K11/34 ,  A61B8/00

CPC分类号： G10K11/348 ,  G01B17/06 ,  G01S15/8918 ,  G01S7/52047

摘要： A PASS ultrasonic system includes a separate receive channel for each respective element in an ultrasonic transducer array which imparts a delay to the echo signal produced by each respective element. The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam which can be readily interpreted even when the transmit beam does not emanate from the center of the array.

摘要翻译： PASS超声波系统包括用于超声换能器阵列中的每个相应元件的单独的接收通道，其对由每个相应元件产生的回波信号施加延迟。 延迟的回波信号被相加以形成转向的动态聚焦和动态窗口的接收波束，即使当发射波束不从阵列的中心发射时，其也可以容易地解释。

公开(公告)号：US4506349A

公开(公告)日：1985-03-19

申请号：US451689

申请日：1982-12-20

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： G11C11/411 ,  G11C11/412 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/108 ,  Y10S257/903

摘要： A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs. Various alternative forms of suitable high impedance leakage current resistances are disclosed, including a resistive sea above the cell and leakage paths included within the gating IGFETs. The high impedance leakage current discharge resistances may be eliminated to provide a dynamic memory cell.

摘要翻译： 一般类型的存储单元采用定义数据节点的一对IGFET和用于存储数据的锁存电路配置的交叉耦合，以及用作传输门的另一对IGFET，用于选择性地将数据耦合到单元或从单元中耦合。 电路技术通过避免在数据节点的充电或放电路径中使用负载电阻器来提供快速的写入速度，并且确保将数据节点完全拉至逻辑高电平或完全拉至逻辑低电平（视情况而定） 而不限于用作传输门的IGFET的栅极和源极端子之间的阈值电压偏移。 包括高阻抗泄漏电流放电电阻，并且仅用于在节点处泄漏泄漏以维持存储器的功能。 在布置的电路配置中，与门控IGFET相比，锁存器IGFET具有相反的沟道导电类型。 公开了适当的高阻抗泄漏电流电阻的各种替代形式，包括在电池单元之上的电阻海和包括在门控IGFET内的泄漏路径。 可以消除高阻抗漏电放电电阻以提供动态存储单元。

公开(公告)号：US4484087A

公开(公告)日：1984-11-20

申请号：US478015

申请日：1983-03-23

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： H03K3/354 ,  H01L27/11 ,  H03K3/356 ,  H03K3/3562 ,  G11C19/28 ,  H03K19/096 ,  H03K23/22

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H03K3/356104 ,  H03K3/35625

摘要： A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node. A cross-coupled switching element comprising a second P-channel IGFET has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node to the voltage supply node. A third P-channel IGFET has its channel arranged to selectively connect the data storage node to the voltage supply node when the cell is disabled. A second N-channel IGFET is arranged to selectively connect the data storage node to the data input node. A high impedance leakage current discharge path electrically connects the data storage node to the one voltage supply node, and discharges any leakage current on the data storage node. The high impedance leakage current discharge path may take a variety of forms, and need not comprise a discrete resistor.

摘要翻译： 在一个实施例中，用于静态触发器应用的五晶体管CMOS静态锁存单元包括具有数据输入节点，数据存储节点，互补数据输出节点，时钟输入节点，用于选择性地使能或 不启用电池，以及一对电源供应节点。 基本上标准的CMOS反相器具有连接到互补数据输出节点的输出。 反相器包括互补的IGFET对，即N沟道IGFET和P沟道IGFET。 N沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到地。 P沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到电压供应节点。 逆变器晶体管栅电极连接到数据存储节点。 包括第二P沟道IGFET的交叉耦合开关元件的栅极连接到互补数据输出节点并被布置成有选择地将数据存储节点连接到电压供应节点。 第三P沟道IGFET具有其通道，其布置成在单元被禁用时选择性地将数据存储节点连接到电压供应节点。 第二N沟道IGFET被布置成选择性地将数据存储节点连接到数据输入节点。 高阻抗泄漏电流放电路径将数据存储节点电连接到一个电压供应节点，并且在数据存储节点上放电任何漏电流。 高阻抗漏电流放电路径可以采取各种形式，并且不需要包括分立电阻器。