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    Address translation through an intermediate address space
    1.
    发明授权
    Address translation through an intermediate address space 有权
    通过中间地址空间进行地址转换

    公开(公告)号：US08966219B2

    公开(公告)日：2015-02-24

    申请号：US11928125

    申请日：2007-10-30

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1063 ,  G06F12/1072

    摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

    摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。

    Read and write aware cache with a read portion and a write portion of a tag and status array
    2.
    发明授权
    Read and write aware cache with a read portion and a write portion of a tag and status array 有权
    具有读取部分和标签和状态数组的写入部分的读写感知高速缓存

    公开(公告)号：US08843705B2

    公开(公告)日：2014-09-23

    申请号：US13572916

    申请日：2012-08-13

    申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

    摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

    摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

    Instruction set architecture extensions for performing power versus performance tradeoffs
    3.
    发明授权
    Instruction set architecture extensions for performing power versus performance tradeoffs 失效
    用于执行功率与性能折衷的指令集架构扩展

    公开(公告)号：US08589665B2

    公开(公告)日：2013-11-19

    申请号：US12788940

    申请日：2010-05-27

    申请人： John B. Carter ,  Jian Li ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    发明人： John B. Carter ,  Jian Li ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/00

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  G06F11/302 ,  G06F11/3062 ,  G06F11/3096

    摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.

    摘要翻译： 提供了用于处理数据处理系统的处理器中的指令的机制。 这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。 这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。 此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

    Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units
    4.
    发明授权
    Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units 失效
    用于动态共享结构以促进多个片上单元的片外通信的技术

    公开(公告)号：US08346988B2

    公开(公告)日：2013-01-01

    申请号：US12786716

    申请日：2010-05-25

    申请人： Jian Li ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F3/00 ,  G06F13/00

    CPC分类号： G06F1/3203 ,  G06F1/3253 ,  G06F9/5011 ,  Y02D10/151 ,  Y02D10/22

    摘要： A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.

    摘要翻译： 一种用于共享一个结构以促进片上单元的片外通信的技术包括：当针对片上单元指示专用结构时，动态分配实现第一通信协议的第一单元到该结构的第一部分。 该技术还包括当为片上单元指示专用结构时，动态地将实现第二通信协议的第二单元分配给该结构的第二部分。 在这种情况下，第一和第二单元集成在相同的芯片中，并且第一和第二协议是不同的。 该技术还包括：当私有结构未被指示用于片上单元时，基于第一单元或第二单元的片外流量要求将第一单元或第二单元动态地分配给该结构的第一和第二部分 。

    Fine Grained Cache Allocation
    5.
    发明申请
    Fine Grained Cache Allocation 有权
    细粒度缓存分配

    公开(公告)号：US20110022773A1

    公开(公告)日：2011-01-27

    申请号：US12509752

    申请日：2009-07-27

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

    摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

    摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

    Techniques for Indirect Data Prefetching
    7.
    发明申请
    Techniques for Indirect Data Prefetching 有权
    间接数据预取技术

    公开(公告)号：US20090198950A1

    公开(公告)日：2009-08-06

    申请号：US12024239

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/02 ,  G06F12/10

    CPC分类号： G06F12/0862 ,  G06F2212/6028

    摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.

    摘要翻译： 处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。 第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。 预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。 第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。 预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。

    DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA
    8.
    发明申请
    DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA 审中-公开
    数据处理系统，处理器和方法，支持部分缓存行数据

    公开(公告)号：US20090198910A1

    公开(公告)日：2009-08-06

    申请号：US12024174

    申请日：2008-02-01

    申请人： RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0831

    摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line.

    摘要翻译： 根据多处理器数据处理系统中的数据处理方法，响应于针对包含多个粒子的数据的高速缓存行的目标颗粒的处理器触摸请求，处理单元起源于多处理器数据处理系统的互连部分触摸 请求仅请求目标颗粒的副本用于后续查询访问。 响应于指示成功的部分触摸请求的组合响应，表示对部分触摸请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒并更新目标颗粒的一致性状态 同时保持高速缓存行的至少另一个颗粒的一致性状态。

    Complier assisted victim cache bypassing
    9.
    发明授权
    Complier assisted victim cache bypassing 失效
    Complier辅助受害者缓存绕过

    公开(公告)号：US07506119B2

    公开(公告)日：2009-03-17

    申请号：US11381563

    申请日：2006-05-04

    申请人： Yaoqing Gao ,  William E. Speight ,  Lixin Zhang

    发明人： Yaoqing Gao ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0888 ,  G06F12/127 ,  Y02D10/13

    摘要： A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused.

    摘要翻译： 一种用于编译器辅助的受害者缓存旁路的方法，包括：将高速缓存行标识为用于受害者缓存旁路的候选者; 向硬件传送绕过受害者缓存信息; 并且检查高速缓存行的状态以确定高速缓存行的修改状态，其中如果在循环或循环嵌套内没有重用的高速缓存行并且不存在立即循环重用或那里，则高速缓存行被识别用于高速缓存绕过 是一个实质的跨循环重用距离，因此它将被重新使用之前被替换为主缓存和受害缓存。

    Latency-tolerant 3D on-chip memory organization
    10.
    发明授权
    Latency-tolerant 3D on-chip memory organization 失效
    延迟容忍的3D片上存储器组织

    公开(公告)号：US08612687B2

    公开(公告)日：2013-12-17

    申请号：US12787895

    申请日：2010-05-26

    申请人： Jian Li ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  William E. Speight ,  Lixin Zhang

    IPC分类号： H01L29/00 ,  H01L21/00 ,  G06F12/00

    CPC分类号： G06F12/0895 ,  G11C8/18

    摘要： A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access.

    摘要翻译： 在3D堆叠存储器组织内提供了一种机制，用于跨多层传播或条带化高速缓存行。 在一个示例组织中，128B高速缓存行在16B宽的总线上需要八个周期。 每层可提供32B。 第一层使用八个传输周期中的前两个发送第一个32B。 下一层使用八个传输周期的接下来的两个周期发送下一个32B，等等。 该机制提供了一个统一的内存访问。