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公开(公告)号：US4363095A
公开(公告)日：1982-12-07
申请号：US221851
申请日：1980-12-31
申请人： William E. Woods , Arthur Peters
发明人： William E. Woods , Arthur Peters
CPC分类号： G06F12/0851
摘要： In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.
摘要翻译： 在数据处理系统中，高速缓冲存储器包括一级和二级偶数和奇数数据存储，以及一级和二级偶数和奇数目录存储。 目录存储包括用于存储与存储在一级和二级偶数和奇数数据存储中的数据字相关联的地址号的最高有效位的多个存储位置。 一级和二级偶数和奇数目录存储由地址号的最低有效位寻址。 比较器电路将存储器请求中提供的地址号码的高位比较与存储在一级偶数和奇数目录中的高位比特存储在由存储器请求中提供的地址的低位比特识别的存储位置处， 低位地址位递增1。 命中检测器电路通过分析比较器的输出来确定所请求的字中的一个，两个，还是没有一个被存储在高速缓冲存储器中。
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公开(公告)号：US4392201A
公开(公告)日：1983-07-05
申请号：US221855
申请日：1980-12-31
CPC分类号： G06F12/0851 , G11C29/26
摘要： A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.
摘要翻译： 高速缓冲存储器，其中由奇数地址号码识别的数据字与偶数地址号码识别的数据字分开存储。 一组诊断控制寄存器提供用于控制高速缓冲存储器内的高速缓存测试的信号，以确定包含在高速缓冲存储器中的各个元件的可操作性。
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公开(公告)号：US4271484A
公开(公告)日：1981-06-02
申请号：US841
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
CPC分类号： G06F9/3885 , G06F11/302 , G06F11/3093 , G06F9/30058 , G06F9/30094
摘要： Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.
摘要翻译： 在指令执行周期期间表示被测状态的过去和现在状态的信号以及表示执行周期的信号被用作施加到存储器的地址信号，所述存储器馈送输出以控制双稳态元件 。 双稳态元件设置为存储器输出信号的状态，并提供表示被测状态的过去状态的地址信号。 存储器被编码以在其输出处响应控制双稳态元件的信号，使得一旦检测到被测状态的给定状态并将其存储在双稳态元件中，则后者被禁止切换，而不管条件下的任何进一步变化如何 在当前指令执行周期内进行测试。
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公开(公告)号：US4224668A
公开(公告)日：1980-09-23
申请号：US864
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
CPC分类号： G06F9/4426
摘要： A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.
摘要翻译： 数据处理器中的控制存储器通过下一个地址生成逻辑来寻址，该地址生成逻辑包括用于寻址控制存储器的第一多路复用器，该多路复用器具有多个输入。 从锁定机构接收这样的输入之一，其允许同时利用多于一个的测试条件来以自由流为基础对控制存储器进行寻址。 这些测试条件以及来自寻址的控制字的信息以多路复用方式用作第一多路复用器的一个输入。 通过使用这种第一多路复用器的其他输入，可以通过使用分支地址信息以及其他测试条件信息来寻址控制存储器。 页面寄存器将页面地址提供给包含在该控制存储器中的多个页面，其中通过使用上述复用器组合寻址每个这样的页面中的位置。
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公开(公告)号：US4494190A
公开(公告)日：1985-01-15
申请号：US377299
申请日：1982-05-12
申请人： Arthur Peters
发明人： Arthur Peters
CPC分类号： G06F12/0831 , G06F15/161
摘要： A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.
摘要翻译： 公开了一种具有多个处理器和/或子处理器，输入/输出（I / O）单元的大型计算机的小型计算机系统，并且包括用于使得能够检测，解码，存储和调度大型和关联处理器之间的数据和指令的逻辑 。 该逻辑检测寻址到其相关联的处理器的信息，并且在独立定时的异步处理器与附加到该大单位的单元之间进行同步。
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6.发明授权Data steering logic for the output of a cache memory having an odd/even bank structure 失效用于输出具有奇数/偶数存储体结构的高速缓冲存储器的数据转向逻辑
公开(公告)号：US4445172A
公开(公告)日：1984-04-24
申请号：US221853
申请日：1980-12-31
申请人： Arthur Peters , Philip E. Stanley
发明人： Arthur Peters , Philip E. Stanley
CPC分类号： G06F12/0851
摘要： A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.
摘要翻译： 一种高速缓冲存储器，包括用于存储与偶数地址号码相关联的数据字的偶数数据存储器和用于存储与奇数地址号码相关联的数据字的奇数数据存储器，用于同时从低位数据字传输低位数据字的本地总线和高位数据字 高速缓冲存储器通过提供单个地址号码请求而请求传送一对数据字的系统元件，以及用于提供与存储器请求号相关联的数据字的数据导向复用器，从奇数或 甚至高速缓存数据存储到本地总线的低阶数据字传送部分，以及从奇数或偶数数据存储器输出到本地总线的高位数据字传送部分的一对数据字中的另一个。
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公开(公告)号：US4272828A
公开(公告)日：1981-06-09
申请号：US842
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
摘要： Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.
摘要翻译： 具有两个独立寄存器文件的算术逻辑设备，每个操作数一个。 每个寄存器文件也与其独立控制的递增和/或递减地址机制相关联。 每个这样的寄存器文件被耦合用于以数字，字节或字为基础进行寻址。 这种装置的操作在从包括在其中也包括这种装置的数据处理器中的控制存储器接收的控制指令的控制下。
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公开(公告)号：US4258420A
公开(公告)日：1981-03-24
申请号：US733
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167 , G06F15/80
CPC分类号： G06F9/3877 , G06F15/8007 , G06F9/3879
摘要： Information from a main data processor is transferred to an auxiliary data processor of the system and is stored in a control file which may be addressed by either a firmware word from a control store or by use of the function code received in an instruction from the main processor. Information in such control file is used for the purpose of addressing main memory. The address for main memory may be incremented or decremented simultaneously as operands are being fetched from main memory for execution.
摘要翻译： 来自主数据处理器的信息被传送到系统的辅助数据处理器，并且被存储在控制文件中，该控制文件可以通过来自控制存储器的固件字来寻址或者通过使用在主指令中接收的功能码 处理器。 这种控制文件中的信息用于寻址主存储器。 当从主存储器中取出操作数进行执行时，主存储器的地址可以同时递增或递减。
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9.发明授权
公开(公告)号：US6140401A
公开(公告)日：2000-10-31
申请号：US776479
申请日：1997-02-27
摘要： The invention concerns the use of a stabilizer combination for polyvinylchloride-based moulding compounds. The stabilizer combination contains (a) at least one solid inorganic component in amounts ranging from 0.3 to 3 parts by weight, relative to 100 parts by weight of polyvinylchloride, selected from sodium aluminosilicates, hydrotalcites and calcium-aluminium-hydroxy-phosphites, and (b) at least one solid or liquid zinc salt in amounts corresponding to a zinc to component (a) ratio of from 0.02 to 0.25 to 1, selected from zinc salts of monocarboxylic acids, substituted or unsubstituted benzoic acid and dicarboxylic acids. This stabilizer combination is used in the production of half-hard and soft polyvinylchloride foils by the calendering process in order to prevent a build-up of coating on the rollers used in this process.
摘要翻译： PCT No.PCT / EP95 / 02776 371日期1997年2月27日 102（e）日期1997年2月27日PCT提交1995年7月14日PCT公布。 公开号WO96 / 03459 日期1996年2月8日本发明涉及用于聚氯乙烯基成型化合物的稳定剂组合物的用途。 稳定剂组合物包含（a）相对于100重量份选自硅铝酸钠，水滑石和钙 - 铝 - 羟基 - 亚磷酸酯的聚氯乙烯的量为0.3-3重量份的至少一种固体无机组分和（ b）至少一种固体或液体锌盐，其量对应于锌至组分（a）的比例为0.02至0.25:1，选自一元羧酸的锌盐，取代或未取代的苯甲酸和二羧酸。 该稳定剂组合用于通过压延方法生产半硬和软的聚氯乙烯箔，以防止在该方法中使用的辊上的涂层积聚。
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公开(公告)号：US5206948A
公开(公告)日：1993-04-27
申请号：US455666
申请日：1989-12-22
申请人： Douglas J. De Angelis , Henry W. J. Maddox , Arthur Peters , Donald J. Rathbun , William L. Saltmarsh
发明人： Douglas J. De Angelis , Henry W. J. Maddox , Arthur Peters , Donald J. Rathbun , William L. Saltmarsh
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3466 , G06F11/349 , G06F11/3495
摘要： A monitoring means for selectively detecting and recording signals representing at selected points within a system, includes trigger generation logic responsive to selected bus signals for generating trigger signals representing the occurrence of selected conditions, and a recording memory for recording the conditions thereupon, a trigger selection logic for selecting trigger outputs corresponding to the trigger signals. The trigger selection logic includes a trigger enabling memory for storing selectable trigger enabling codes, wherein each enabling code corresponds to a trigger signal, and trigger output logic responsive to the trigger enabling codes and to the trigger signals for providing trigger outputs. The trigger enabling codes include bus enabling codes representing selected conditions on a bus of the system, trigger sequence enabling codes corresponding to sequential combinations of trigger signals and external trigger enabling codes corresponding to triggers external to the system. The enabling codes may select trigger signals to be used in logical AND or OR functions in generating a trigger output or in substitution for a bus trigger signal.
摘要翻译： 用于选择性地检测和记录表示在系统内的选定点处的信号的监视装置包括响应于所选择的总线信号的触发生成逻辑，用于产生表示所选条件出现的触发信号，以及用于记录其上的条件的记录存储器，触发选择 用于选择与触发信号对应的触发输出的逻辑。 触发选择逻辑包括触发器，用于存储可选择的触发使能代码，其中每个使能代码对应于触发信号，并且响应于触发使能代码和触发信号触发输出逻辑以提供触发输出。 触发使能代码包括表示系统总线上的选定条件的总线使能代码，触发序列使能对应于触发信号的顺序组合的代码和对应于系统外部的触发的外部触发使能代码。 启用代码可以选择在逻辑“或”或“或”功能中使用的触发信号来产生触发输出或代替总线触发信号。
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