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    VARACTOR
    2.
    发明申请
    VARACTOR 审中-公开
    变量

    公开(公告)号：US20110291171A1

    公开(公告)日：2011-12-01

    申请号：US13050043

    申请日：2011-03-17

    申请人： John J. Pekarik ,  William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Yun Shi ,  Yanli Zhang

    发明人： John J. Pekarik ,  William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Yun Shi ,  Yanli Zhang

    IPC分类号： H01L29/92 ,  H01L21/8234

    CPC分类号： H01L29/93 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/78

    摘要： A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated.

    摘要翻译： 一种包括多个FET的可变电容器件，每个FET的源极和漏极耦合到第一端子，每个FET的栅极耦合到第二端子，所述器件在所述第一和第二端子之间的电容变化为 所述器件还包括偏置电路，为每个FET提供相应的背栅极偏置电压，从而设置其相应的栅极阈值电压。 可以在设计时或动态地根据需要调整总体V-C特性。 形成变容二极管的FET数量越多，可以单独设置的可能的Vt值的数量就越多，从而可以更接近任意的V-C特性。

    Self aligned structures and design structure thereof
    3.
    发明授权
    Self aligned structures and design structure thereof 失效
    自对准结构及其设计结构

    公开(公告)号：US08552532B2

    公开(公告)日：2013-10-08

    申请号：US13343287

    申请日：2012-01-04

    申请人： William F. Clark, Jr. ,  John J. Pekarik ,  Yun Shi ,  Yanli Zhang

    发明人： William F. Clark, Jr. ,  John J. Pekarik ,  Yun Shi ,  Yanli Zhang

    IPC分类号： H01L29/1004

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/732

    摘要： Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.

    摘要翻译： 垂直双极结结构，制造方法和设计结构。 该方法包括在芯片的第一区域中形成用于双极结型晶体管（BJT）的一个或多个牺牲结构。 该方法包括在一个或多个牺牲结构上形成掩模。 该方法还包括蚀刻掩模中与该一个或多个牺牲结构对准的开口。 该方法包括通过该开口形成沟槽并延伸到一个或多个牺牲结构下方的扩散区域中。 该方法包括通过在沟槽中沉积与扩散区接触的外延材料来形成BJT的基极区域。 该方法包括通过在沟槽内的基极区域上沉积第二外延材料来形成发射极接触。 用于发射极区域的外延材料具有与基极区域的外延材料相反的掺杂剂类型。

    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
    4.
    发明授权
    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
    集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构

    公开(公告)号：US09041105B2

    公开(公告)日：2015-05-26

    申请号：US13553947

    申请日：2012-07-20

    申请人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    发明人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

    摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

    INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE
    5.
    发明申请
    INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE 有权
    集成电路，包括在绝缘体上的晶体管结构，相关方法和设计结构

    公开(公告)号：US20140021547A1

    公开(公告)日：2014-01-23

    申请号：US13553947

    申请日：2012-07-20

    申请人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    发明人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  H01L21/265

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

    摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

    BICMOS DEVICES ON ETSOI
    6.
    发明申请
    BICMOS DEVICES ON ETSOI 审中-公开
    BICMOS设备在ETSOI

    公开(公告)号：US20130277753A1

    公开(公告)日：2013-10-24

    申请号：US13451806

    申请日：2012-04-20

    申请人： William F. Clark, JR. ,  Qizhi Liu ,  Robert Mark Rassel ,  Yun Shi

    发明人： William F. Clark, JR. ,  Qizhi Liu ,  Robert Mark Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/8249

    CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/1203

    摘要： A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.

    摘要翻译： 提供BiCMOS器件结构，其制造方法及其设计结构。 BiCMOS器件结构包括在绝缘层上具有半导体材料层的衬底。 BiCMOS器件结构还包括形成在衬底的第一区域中的双极结型晶体管结构，其具有至少部分地由半导体材料层的一部分形成的非本征基极层。

    Field effect transistor and method of manufacture
    7.
    发明授权
    Field effect transistor and method of manufacture 有权
    场效应晶体管及其制造方法

    公开(公告)号：US08921190B2

    公开(公告)日：2014-12-30

    申请号：US12099175

    申请日：2008-04-08

    申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

    发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

    IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66

    CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

    摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

    摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

    FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE
    9.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20090250772A1

    公开(公告)日：2009-10-08

    申请号：US12099175

    申请日：2008-04-08

    申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

    发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

    摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

    摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。