-
公开(公告)号：US07185185B2
公开(公告)日：2007-02-27
申请号：US10403406
申请日：2003-03-31
IPC分类号： G06F12/12
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译： 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中，多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。 水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。
-
公开(公告)号：US06694347B2
公开(公告)日：2004-02-17
申请号：US10074419
申请日：2002-02-12
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
-
公开(公告)号：US06507862B1
公开(公告)日：2003-01-14
申请号：US09309735
申请日：1999-05-11
IPC分类号： G06F946
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
-
公开(公告)号：US07587581B2
公开(公告)日：2009-09-08
申请号：US11710112
申请日：2007-02-23
IPC分类号： G06F9/38
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译： 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中，多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。 水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。
-
5.发明授权Vertically and horizontally threaded processor with multidimensional storage for storing thread data 有权垂直和水平线程处理器，具有用于存储线程数据的多维存储公开(公告)号：US06351808B1
公开(公告)日：2002-02-26
申请号：US09309731
申请日：1999-05-11
IPC分类号： G06F946
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3013 , G06F9/3802 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.
摘要翻译： 处理器包括一个“四维”寄存器结构，其中寄存器堆栈结构由N复制用于与三维存储电路结合的垂直线程。 多维存储器通过构造诸如寄存器文件或存储器的存储器来形成为多个二维存储平面。
-
6.发明授权公开(公告)号：US06801997B2
公开(公告)日：2004-10-05
申请号：US10154076
申请日：2002-05-23
IPC分类号： G06F938
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
摘要翻译： 处理器包括用于标记线程标识符（TID）的逻辑，用于未被停止的处理器块的使用。 相关的非停滞块包括缓存，翻译后备缓冲器（TLB），加载缓冲器异步接口，外部存储器管理单元（MMU）接口等。 处理器包括分离成多个N个高速缓存部分的高速缓存。 缓存隔离避免线程间的干扰，“污染”或“串扰”。 用于缓存分离的一种技术利用用于存储和传送线程标识（TID）位的逻辑。 缓存使用高速缓存索引逻辑。 例如，TID位可以插入高速缓存索引的最高有效位。
-
公开(公告)号：US06542991B1
公开(公告)日：2003-04-01
申请号：US09309734
申请日：1999-05-11
IPC分类号： G06F1212
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
-
公开(公告)号：US07316021B2
公开(公告)日：2008-01-01
申请号：US10779944
申请日：2004-02-17
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
摘要翻译： 处理器包括用于通过响应于异常情况调用多线程类型功能来执行非线程程序来获得非常快速的异常处理功能的逻辑。 处理器在多线程状态下运行或执行非线程程序时，在执行过程中会经历多个机器状态。 非常快的异常处理逻辑包括将异常信号线连接到线程选择逻辑，导致异常信号引起线程和机器状态的开关。 线程和机器状态的切换使得处理器立即进入并退出异常处理程序，而不用等待排除流水线或队列，并且没有操作系统的软件保存和恢复寄存器的固有时间损失。
-
公开(公告)号：US06938147B1
公开(公告)日：2005-08-30
申请号：US09309732
申请日：1999-05-11
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译： 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中，多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。 水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。
-
公开(公告)号：US06341347B1
公开(公告)日：2002-01-22
申请号：US09309733
申请日：1999-05-11
IPC分类号： G06F930
CPC分类号： G06F9/4843 , G06F9/3851 , G06F12/0897
摘要： A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-switching operation is “oblivious” thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling. The oblivious technique avoids usage of an extra global interconnection between threads for thread selection. A second thread-switching operation is “semi-oblivious” thread-switching for use with an existing “pipeline stall” signal (if any). The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided. A third thread-switching operation is an “intelligent global scheduler” thread-switching in which a thread switch decision is based on a plurality of signals including: (1) an L1 data cache miss stall signal, (2) an instruction buffer empty signal, (3) an L2 cache miss signal, (4) a thread priority signal, (5) a thread timer signal, (6) an interrupt signal, or other sources of triggering. In some embodiments, the thread select signal is broadcast as fast as possible, similar to a clock tree distribution. In some systems, a processor derives a thread select signal that is applied to the flip-flops by overloading a scan enable (SE) signal of a scannable flip-flop.
摘要翻译： 处理器包括线程切换控制逻辑，其响应于L1高速缓存未命中而执行快速线程切换操作。 快速线程切换操作实现了几种线程切换方法中的一种或多种。 第一个线程切换操作对于每个N个周期是“忽视的”线程切换，其中各个触发器本地确定线程切换而不通知失速。 遗忘的技术避免了在线程选择的线程之间使用额外的全局互连。 第二个线程切换操作是与现有的“流水线失速”信号（如果有的话）一起使用的“半隐匿”线程切换。 流水线失速信号以两个容量运行，首先作为流水线停顿的通知，第二个作为线程之间的线程选择信号，这样就可以避免线程选择线程之间额外的全局互连使用。 第三线程切换操作是“智能全局调度器”线程切换，其中线程切换决定基于多个信号，包括：（1）L1数据高速缓存未命中停止信号，（2）指令缓冲器空信号 ，（3）L2高速缓存未命中信号，（4）线程优先信号，（5）线程定时器信号，（6）中断信号或其他触发源。 在一些实施例中，类似于时钟树分布，尽可能快地广播线程选择信号。 在一些系统中，处理器通过过载可扫描触发器的扫描使能（SE）信号来导出施加到触发器的线程选择信号。
-
-
-
-
-
-
-
-
-
搜索结果
34 条记录 (耗时 0.032 秒)
