公开(公告)号：US20070121262A1

公开(公告)日：2007-05-31

申请号：US11287615

申请日：2005-11-28

申请人： William Loh ,  Minxuan Liu ,  Jau-Wen Chen

发明人： William Loh ,  Minxuan Liu ,  Jau-Wen Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

摘要翻译： 一种静电放电保护电路，适于减少集成电路线上的静电放电事件。 保护电路包括具有电连接到该线路的源极触点的NMOS晶体管。 漏极触点电连接到逻辑低电压，并且栅极触点也通过电阻器电连接到逻辑低电压。 衬底偏置泵电连接到NMOS晶体管的背栅极，其中当没有静电放电事件时，偏压泵在集成电路的正常操作期间提供稳态直流负偏压。

公开(公告)号：US07379281B2

公开(公告)日：2008-05-27

申请号：US11287615

申请日：2005-11-28

申请人： William M. Loh ,  Minxuan Liu ,  Jau-Wen Chen

发明人： William M. Loh ,  Minxuan Liu ,  Jau-Wen Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

摘要翻译： 一种静电放电保护电路，适于减少集成电路线上的静电放电事件。 保护电路包括具有电连接到该线路的源极触点的NMOS晶体管。 漏极触点电连接到逻辑低电压，并且栅极触点也通过电阻器电连接到逻辑低电压。 衬底偏置泵电连接到NMOS晶体管的背栅极，其中当没有静电放电事件时，偏压泵在集成电路的正常操作期间提供稳态直流负偏压。

公开(公告)号：US20070138973A1

公开(公告)日：2007-06-21

申请号：US11300938

申请日：2005-12-15

申请人： William Loh ,  Choshu Ito ,  Jau-Wen Chen

发明人： William Loh ,  Choshu Ito ,  Jau-Wen Chen

IPC分类号： H05B37/00

CPC分类号： H01L27/0248

摘要： An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

摘要翻译： 对具有易受静电放电损坏的功能电路的类型的数字集成电路的改进。 静电放电保护元件与功能电路串联放置并且设置在来自功能电路的电流的正常方向的上游。 静电放电保护元件包括具有热失控的电阻扼流圈和感应扼流圈中的至少一个。

公开(公告)号：US20070019345A1

公开(公告)日：2007-01-25

申请号：US11174135

申请日：2005-06-30

申请人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

发明人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

摘要翻译： 一种用于保护电路的系统和方法。 该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。 逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。 根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。 此外，保护电路保护电路免受常规FET无法保护的ESD事件。

公开(公告)号：US20070018670A1

公开(公告)日：2007-01-25

申请号：US11187401

申请日：2005-07-21

申请人： Choshu Ito ,  William Loh ,  Jau-Wen Chen

发明人： Choshu Ito ,  William Loh ,  Jau-Wen Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/002

摘要： The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.

摘要翻译： 本发明提供一种用于静电放电（ESD）测试的系统和方法。 该系统包括电路，其具有耦合到被测器件（DUT）的输入/输出（I / O）电路的开关，耦合到开关的电荷源和耦合到开关的控制电路，其中控制 电路接通开关以将ESD电流从电荷源放电到I / O电路，并且其中电路集成到DUT中。 根据本文公开的系统和方法，该系统提供DUT的片上ESD测试，而不需要昂贵且专门的测试设备。

公开(公告)号：US07777996B2

公开(公告)日：2010-08-17

申请号：US11174135

申请日：2005-06-30

申请人： William M. Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

发明人： William M. Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

摘要翻译： 一种用于保护电路的系统和方法。 该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。 逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。 根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。 此外，保护电路保护电路免受常规FET无法保护的ESD事件。

公开(公告)号：US07763908B2

公开(公告)日：2010-07-27

申请号：US11189217

申请日：2005-07-25

申请人： Jau-Wen Chen

发明人： Jau-Wen Chen

IPC分类号： H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.

摘要翻译： 一种可控硅整流装置，包括基板，配置有低压触发的可硅可控整流器。 多个触发元件（例如，NMOS指）形成在基板上并与低电压触发的可硅可控整流器集成，其中多个触发元件被插入到低电压触发的可硅可控整流器中，以便 允许低电压触发的可控硅整流器在人体模型和充电器件模型应力事件中防止静电放电。

公开(公告)号：US07317228B2

公开(公告)日：2008-01-08

申请号：US11055145

申请日：2005-02-10

申请人： Jau-Wen Chen

发明人： Jau-Wen Chen

IPC分类号： H01L23/62

CPC分类号： H01L29/0847 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small, as this can improve a non-uniform silicidation process. The resistance of the segmented diffusion resistors is determined by their width and length, and effectively increases the ballasting effect of parasitic n-p-n bipolar transistors.

摘要翻译： 在全硅化CMOS工艺中使用自镇流ESD保护技术设计和优化NMOS驱动器。 硅化NMOS手指，包括分段漏极扩散。 具体地，分段漏极扩散提供了自镇流电阻器，其改善了ESD性能。 优选地，每个扩散电阻器的宽度相对较小，因为这可以改善不均匀的硅化工艺。 分段扩散电阻器的电阻由其宽度和长度决定，并有效地增加了寄生n-p-n双极晶体管的镇流效应。

公开(公告)号：US06347026B1

公开(公告)日：2002-02-12

申请号：US09320013

申请日：1999-05-26

申请人： Roberto Sung ,  Jau-Wen Chen

发明人： Roberto Sung ,  Jau-Wen Chen

IPC分类号： H02H900

CPC分类号： H01L27/0251

摘要： Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal. In response to the current flow through the inter-transistor node, the lateral bipolar transistor substantially increases the current flow from the first terminal, through the lateral bipolar transistor, and to the second terminal so that a majority of current will flow through this path. Similarly, when an ESD pulse appears on the second terminal, this creates current flow from the second terminal, through the collector-base junction of the lateral bipolar transistor, through the inter-transistor node, through the diode, and to the first terminal.

摘要翻译： 使用包括使用杀螨剂的互补金属氧化物半导体工艺制造，用于集成电路的输入和电源保护电路保护电压和信号端子免受过电压和ESD脉冲的影响。 连接的二极管连接在第一端子和晶体管间节点之间，场效应晶体管连接在晶体管间节点和第二端子之间，并且具有连接到晶体管间节点的基极的横向双极晶体管， 连接在第一和第二端子之间。 当ESD脉冲出现在第一端子上时，晶体管间节点处的电压增加，直到达到场效应晶体管的快速恢复触发电压，随后电流从第一端子流过横向双极晶体管的发射极 - 基极结 ，通过晶体管间节点，通过场效应晶体管和第二端子。 响应于通过晶体管间晶体管节点的电流，横向双极晶体管基本上增加了来自第一端子的电流，通过横向双极晶体管和第二端子，使得大部分电流将流过该路径。 类似地，当ESD脉冲出现在第二端子上时，这产生来自第二端子，横向双极晶体管的集电极 - 基极结，通过晶体管间节点，通过二极管和第一端子的电流。

公开(公告)号：US07551414B2

公开(公告)日：2009-06-23

申请号：US11300938

申请日：2005-12-15

申请人： William M. Loh ,  Choshu Ito ,  Jau-Wen Chen

发明人： William M. Loh ,  Choshu Ito ,  Jau-Wen Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

摘要翻译： 对具有易受静电放电损坏的功能电路的类型的数字集成电路的改进。 静电放电保护元件与功能电路串联放置并且设置在来自功能电路的电流的正常方向的上游。 静电放电保护元件包括具有热失控的电阻扼流圈和感应扼流圈中的至少一个。