公开(公告)号：US20070019345A1

公开(公告)日：2007-01-25

申请号：US11174135

申请日：2005-06-30

申请人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

发明人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

摘要翻译： 一种用于保护电路的系统和方法。 该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。 逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。 根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。 此外，保护电路保护电路免受常规FET无法保护的ESD事件。

公开(公告)号：US20070138973A1

公开(公告)日：2007-06-21

申请号：US11300938

申请日：2005-12-15

申请人： William Loh ,  Choshu Ito ,  Jau-Wen Chen

发明人： William Loh ,  Choshu Ito ,  Jau-Wen Chen

IPC分类号： H05B37/00

CPC分类号： H01L27/0248

摘要： An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

摘要翻译： 对具有易受静电放电损坏的功能电路的类型的数字集成电路的改进。 静电放电保护元件与功能电路串联放置并且设置在来自功能电路的电流的正常方向的上游。 静电放电保护元件包括具有热失控的电阻扼流圈和感应扼流圈中的至少一个。

公开(公告)号：US20070018670A1

公开(公告)日：2007-01-25

申请号：US11187401

申请日：2005-07-21

申请人： Choshu Ito ,  William Loh ,  Jau-Wen Chen

发明人： Choshu Ito ,  William Loh ,  Jau-Wen Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/002

摘要： The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.

摘要翻译： 本发明提供一种用于静电放电（ESD）测试的系统和方法。 该系统包括电路，其具有耦合到被测器件（DUT）的输入/输出（I / O）电路的开关，耦合到开关的电荷源和耦合到开关的控制电路，其中控制 电路接通开关以将ESD电流从电荷源放电到I / O电路，并且其中电路集成到DUT中。 根据本文公开的系统和方法，该系统提供DUT的片上ESD测试，而不需要昂贵且专门的测试设备。

公开(公告)号：US20070121262A1

公开(公告)日：2007-05-31

申请号：US11287615

申请日：2005-11-28

申请人： William Loh ,  Minxuan Liu ,  Jau-Wen Chen

发明人： William Loh ,  Minxuan Liu ,  Jau-Wen Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

摘要翻译： 一种静电放电保护电路，适于减少集成电路线上的静电放电事件。 保护电路包括具有电连接到该线路的源极触点的NMOS晶体管。 漏极触点电连接到逻辑低电压，并且栅极触点也通过电阻器电连接到逻辑低电压。 衬底偏置泵电连接到NMOS晶体管的背栅极，其中当没有静电放电事件时，偏压泵在集成电路的正常操作期间提供稳态直流负偏压。

公开(公告)号：US20100194616A1

公开(公告)日：2010-08-05

申请号：US12669481

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H03M1/12

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。 第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。 第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。 至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个， 子级交错。 在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和 第四子电平交错同步到第一时钟相位。

公开(公告)号：US20090296292A1

公开(公告)日：2009-12-03

申请号：US12128108

申请日：2008-05-28

申请人： Tze Wee Chen ,  William Loh ,  Choshu Ito

发明人： Tze Wee Chen ,  William Loh ,  Choshu Ito

IPC分类号： H02H9/00 ,  H01H59/00

CPC分类号： H01H59/0009 ,  H02H9/046

摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.

摘要翻译： 用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。 在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。 在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。 第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。

公开(公告)号：US08798981B2

公开(公告)日：2014-08-05

申请号：US12143895

申请日：2008-06-23

申请人： Choshu Ito ,  William Loh

发明人： Choshu Ito ,  William Loh

IPC分类号： G06G7/56 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/50 ,  G06F17/5009 ,  G06F17/5045

摘要： A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.

摘要翻译： 用于模拟电路对应用于电路的ESD输入激励的响应的方法包括以下步骤：将电路的描述接收到电路仿真程序中，该电路包括指示在该电路中的磁耦合的至少一个互感元件 电路 在非线性元件的各个DC偏置点处产生电路中的非线性元件的线性近似; 获得电路的频域传递函数; 获得电路的时域脉冲响应作为频域传递函数的函数; 积分时域脉冲响应以产生电路的阶跃响应，阶跃响应指示电路对ESD输入刺激的响应; 以及分析电路的阶跃响应以确定电路是否将在对应于电路的规定参数内运行。

公开(公告)号：US20100100859A1

公开(公告)日：2010-04-22

申请号：US12255002

申请日：2008-10-21

申请人： Choshu Ito ,  Tze Wee Chen ,  William Loh

发明人： Choshu Ito ,  Tze Wee Chen ,  William Loh

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5036 ,  G06F2217/72 ,  G06F2217/82

摘要： A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.

摘要翻译： 一种防止CDM ESD事件引起功能故障的设计方法。 晶体管模型用于对细胞的最终状态建模，然后使用模拟器来识别不可侵入的细胞。 然后鉴定潜在的故障部位的细胞。 被识别为潜在受害者的细胞由具有相同逻辑功能的先前识别的无形细胞所取代。 另一方面，如果不能发现具有相同功能的单元，则可以在潜在的牺牲晶体管的前面插入不可变缓冲单元（不会影响逻辑功能）作为保护。 通过用已被确定为无害的细胞代替所有潜在的受害细胞，所得到的设计将被保证是CDM耐受性的。

公开(公告)号：US20100195776A1

公开(公告)日：2010-08-05

申请号：US12669482

申请日：2008-06-06

申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

IPC分类号： H04L7/02 ,  H03K5/153

CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。 该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。 选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。 从所选择的输出中导出第一交错输出。 锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。 选择器输入包括锁存器的输出。

公开(公告)号：US20060245127A1

公开(公告)日：2006-11-02

申请号：US11349358

申请日：2006-02-07

申请人： Choshu Ito ,  Li Ooi ,  William Loh

发明人： Choshu Ito ,  Li Ooi ,  William Loh

IPC分类号： H02H9/00

CPC分类号： G06F17/5036

摘要： Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.

摘要翻译： 改进CDM ESD事件仿真和修复电路设计的方法和结构，以纠正由此类事件引起的应用电路设计对核心电路的以前不可思议的损害。 本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。 根据其特征和方面的改进的仿真技术可以预测这种感应耦合可能会对核心电路造成损害。 本发明的其它特征和方面可以改变应用电路设计，以通过将附加的缓冲电路自动插入到可能受这种电感耦合影响的核心电路的芯线迹来提供补救。