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    Data processing system having centralized memory refresh
    1.
    发明授权
    Data processing system having centralized memory refresh 失效
    数据处理系统具有集中的内存刷新

    公开(公告)号：US4317169A

    公开(公告)日：1982-02-23

    申请号：US12081

    申请日：1979-02-14

    申请人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

    发明人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

    IPC分类号： G06F12/00 ,  G11C11/406 ,  G06F13/00

    CPC分类号： G11C11/406

    摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

    摘要翻译： 在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号， 可以执行存储器刷新操作。 逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。 此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。 在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

    Data processing system having centralized nonexistent memory address detection
    2.
    发明授权
    Data processing system having centralized nonexistent memory address detection 失效
    数据处理系统具有集中的不存在的存储器地址检测

    公开(公告)号：US4340933A

    公开(公告)日：1982-07-20

    申请号：US8010

    申请日：1979-02-12

    申请人： Ming T. Miu ,  John J. Bradley ,  William Panepinto, Jr. ,  Jian-Kuo Shen

    发明人： Ming T. Miu ,  John J. Bradley ,  William Panepinto, Jr. ,  Jian-Kuo Shen

    IPC分类号： G06F12/06 ,  G06F13/362 ,  G06F11/00 ,  G06F13/00

    CPC分类号： G06F13/362 ,  G06F12/0684

    摘要： In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.

    摘要翻译： 在包括具有连接有用于存储程序软件指令和程序数据的一个或多个主存储单元的一个或多个公共总线的中央处理单元（CPU）的数据处理系统中，在CPU内提供逻辑，以检测尝试 访问未包含在数据处理系统中存在的一个或多个主存储器单元中的主存储器位置。 提供逻辑用于检测在CPU执行软件指令的过程中进行访问的情况下的访问不存在的存储器位置的尝试，或者在执行访问以在主存储器之间传送数据的情况下 以及连接到所述一个或多个公共总线中的一个的输入/输出控制器。

    Data processing system having centralized data alignment for I/O controllers
    10.
    发明授权
    Data processing system having centralized data alignment for I/O controllers 失效
    数据处理系统具有I / O控制器的集中数据对齐

    公开(公告)号：US4321665A

    公开(公告)日：1982-03-23

    申请号：US8121

    申请日：1979-01-31

    申请人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

    发明人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

    IPC分类号： G06F13/40 ,  G06F3/00

    CPC分类号： G06F13/4013

    摘要： In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

    摘要翻译： 在包括中央处理单元（CPU）的数据处理系统中，主存储器和连接到公共总线信息的多个输入/输出控制器（IOC）可以在主存储器和CPU以及主存储器和IOC之间传送。 在CPU内部提供逻辑，以便在公共总线的数据线上对齐一个数据字节，使得它可以从主存储器从数据线中取出，并写入多字节字而无需进一步对齐。 在CPU中提供逻辑以从从主存储器读取的数据的多字节字提取出公共总线数据线上相应的数据字节并将其对准在公共总线数据线上，使得IOC可以传递数据 字节到外围设备，无需进一步对齐。