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    High-throughput interface between a system memory controller and a peripheral device
    5.
    发明授权
    High-throughput interface between a system memory controller and a peripheral device 有权

    公开(公告)号：US06434692B1

    公开(公告)日：2002-08-13

    申请号：US09792496

    申请日：2001-02-23

    申请人： Norman J. Rasmussen ,  William S. Wu

    发明人： Norman J. Rasmussen ,  William S. Wu

    IPC分类号： G06F1338

    摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

    High-throughput interface between a system memory controller and a peripheral device
    7.
    发明授权
    High-throughput interface between a system memory controller and a peripheral device 有权
    系统内存控制器和外围设备之间的高吞吐量接口

    公开(公告)号：US06266719B1

    公开(公告)日：2001-07-24

    申请号：US09656192

    申请日：2000-09-06

    申请人： Norman J. Rasmussen ,  William S. Wu

    发明人： Norman J. Rasmussen ,  William S. Wu

    IPC分类号： G06F1328

    CPC分类号： G06F3/14 ,  G06F13/126

    摘要： A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

    摘要翻译： 高通量存储器访问接口允许系统内存控制器和视频/图形适配器之间的数据传输速率高于使用标准本地总线架构的数据传输速率。 该接口使数据可以以两种可选速度中的任意一种直接写入外围设备。 外围设备可以是图形适配器。 指示适配器的写入缓冲器是否满的信号用于确定到适配器的写入事务是否可以进行。 如果事务当时无法继续，则可以在界面中排队。

    Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions
    10.
    发明申请
    Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions 审中-公开
    非易失性存储器和小逻辑组的方法分布在主动SLC和MLC内存分区中

    公开(公告)号：US20120297121A1

    公开(公告)日：2012-11-22

    申请号：US13468720

    申请日：2012-05-10

    申请人： Sergey Anatolievich Gorobets ,  William S. Wu ,  Steven T. Sprouse

    发明人： Sergey Anatolievich Gorobets ,  William S. Wu ,  Steven T. Sprouse

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C2211/5641

    摘要： A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM.

    摘要翻译： 组织成闪存可擦除块的非易失性存储器通过在写入块之前先进入逻辑组，从主机写入中接收数据。 每个逻辑组包含来自预定义的一组订单逻辑地址的数据，并且具有小于块的固定大小。 通过将主机的逻辑地址空间划分为有序逻辑地址的非重叠子范围来获得逻辑组的总和，每个逻辑组在由至少一个页面的最小大小限定的范围内具有预定大小，并且 在块中拟合至少两个逻辑组的最大大小，并且高达主机写入的典型大小高达一个数量级。 以这种方式，避免了由于操作大的逻辑组而导致的过多垃圾收集，同时减少了地址空间以最小化缓存RAM的大小。