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公开(公告)号：US5761212A
公开(公告)日：1998-06-02
申请号：US545965
申请日：1995-10-20
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values. The measurement circuit also includes a conversion circuit for converting the test pattern to a sequence of expected sample values in accordance with a state machine model of the sequence detector. The sample value error results from a comparison of the readback sample value to the expected sample value.
摘要翻译： 提供测量电路以获得用于从数字读取通道监视性能的数据。 包括序列检测器的数字读通道的元件与测量电路一起并入集成电路中。 测量电路将来自磁存储装置的回读数据的数字化样本与周围样品相关联，使得可以根据其周围环境收集特定样品。 该电路包括可重复打开以供数据采集的可编程时间窗口。 电路设计用于收集各种类型的数据，包括误码率，采样值，平方采样误差，平方增益误差，平方定时误差，以及采样误差超出可接受的可编程阈值时的出现。 测量电路包括用于产生测试图案的信号发生器，其首先被存储然后被读取以产生数字化的回读采样值。 测量电路还包括根据序列检测器的状态机模型将测试图案转换成预期样本值序列的转换电路。 样本值误差来自于回读样本值与预期样本值的比较。
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2.发明授权Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration 失效信道质量电路采用采样幅度读取通道中的测试码型发生器进行校准
公开(公告)号：US6005731A
公开(公告)日：1999-12-21
申请号：US844174
申请日：1997-04-18
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
摘要翻译： 一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作， 估计存储系统的误码率，并检测磁介质中的缺陷。 信道质量电路产生写入存储系统的数字数据的测试模式。 然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。 测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。 门控逻辑被编程为仅累积感兴趣的特定性能数据。 信道质量电路计算自动和互相关，平方误差和阈值比较。 缺陷检测滤波器检测介质中的特定缺陷。 为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。
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公开(公告)号：US5987634A
公开(公告)日：1999-11-16
申请号：US897339
申请日：1997-07-21
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
摘要翻译： 一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作， 估计存储系统的误码率，并检测磁介质中的缺陷。 信道质量电路产生写入存储系统的数字数据的测试模式。 然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。 测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。 门控逻辑被编程为仅累积感兴趣的特定性能数据。 信道质量电路计算自动和互相关，平方误差和阈值比较。 缺陷检测滤波器检测介质中的特定缺陷。 为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。
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公开(公告)号：US5754353A
公开(公告)日：1998-05-19
申请号：US340939
申请日：1994-11-17
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/18 , G11B20/1816 , G11B20/182
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
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5.发明授权Sampled amplitude read channel employing interpolated timing recovery and a remod/demod sequence detector 失效采用内插定时恢复的采样幅度读取通道和重构/解调序列检测器
公开(公告)号：US5771127A
公开(公告)日：1998-06-23
申请号：US681678
申请日：1996-07-29
申请人： David E. Reed , William R. Foland, Jr. , William G. Bliss , Richard T. Behrens , Lisa C. Sundell
发明人： David E. Reed , William R. Foland, Jr. , William G. Bliss , Richard T. Behrens , Lisa C. Sundell
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1426
摘要： In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.
摘要翻译： 在用于记录二进制数据的计算机磁盘存储系统中，采样幅度读取通道包括用于从位于盘存储介质上的读取头的模拟读取信号中异步采样脉冲的采样装置，用于产生同步采样值的内插定时恢复，以及 序列检测器，用于从同步样本值检测二进制数据。 序列检测器包括用于检测可能包含位错误的初步二进制序列的解调器，用于重新调制到估计样本值的再调制器，用于产生采样误差值的装置，用于检测位错误的误差模式检测器，错误检测验证器， 以及用于校正位错误的纠错器。 再调制器包括部分擦除电路，其补偿由位于主脉冲附近的次级脉冲引起的初级脉冲的幅度的非线性减小。 误差模式检测器包括峰值误差模式检测器，并且如果检测到错误模式，则用于禁止错误模式检测器的装置，直到检测到的错误模式被完全处理为止。 错误检测验证器检查检测到的错误事件的有效性，如果有效，则允许错误校正器的操作。
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6.发明授权Circuits, architectures, apparatuses, systems, algorithms and methods and software for timing calibration for optical disc recording 有权用于光盘记录的定时校准的电路，架构，设备，系统，算法和方法以及软件公开(公告)号：US08498186B2
公开(公告)日：2013-07-30
申请号：US12352924
申请日：2009-01-13
CPC分类号： G11B7/1267 , G11B7/00456 , G11B20/10009 , G11B2220/2537
摘要： The present disclosure relates to methods, software, and apparatuses for correcting reading and/or writing operations in an optical storage medium. The methods generally include reading a region of an optical storage medium to produce a readback signal, measuring timing offsets for a plurality of the data edges (including one or more non-guide edges), and storing an offset correction for at least one of the plurality of edges based on a measured offset of at least one of the plurality of edges relative to a predetermined offset. The disclosure advantageously enables precise measurement of timing offsets in optical storage media and correction of the measured offsets for timing offsets attributable to edge jitter, timing loop drift, or factors independent of variations in the medium and/or write operation characteristics.
摘要翻译： 本公开涉及用于校正光学存储介质中的读取和/或写入操作的方法，软件和装置。 所述方法通常包括读取光学存储介质的区域以产生回读信号，测量多个数据边缘（包括一个或多个非引导边缘）的定时偏移，以及存储对于至少一个 基于所述多个边缘中的至少一个相对于预定偏移的测量的偏移量的多个边缘。 该公开有利地能够精确测量光学存储介质中的定时偏移，并校正由于边缘抖动，定时环路漂移或独立于介质和/或写入操作特性的变化的因素的定时偏移的测量偏移。
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7.发明授权Circuits, architectures, apparatuses, systems, algorithms and methods and software for optimum power calibration for optical disc recording 失效电路，架构，设备，系统，算法和方法和软件，用于光盘记录的最佳功率校准公开(公告)号：US08559284B1
公开(公告)日：2013-10-15
申请号：US12352950
申请日：2009-01-13
CPC分类号： G11B20/10009 , G11B7/1267 , G11B20/10027 , G11B20/1217 , G11B2020/1275 , G11B2220/2537
摘要： Methods, software, and apparatuses for reading from and/or writing to an optical storage medium. The methods generally include steps for reading a region of an optical storage medium to produce a readback signal, processing predetermined pattern data to produce one or more measurement instructions, measuring one or more characteristics of the readback signal in response to the measurement instructions to produce one or more measurement results, and further processing the readback signal in accordance with one or more of the measurement results. Thus, the ability to flexibly set test parameters and to quickly and accurately test the write characteristics of a recordable or re-writable optical storage medium is provided.
摘要翻译： 用于从光学存储介质读取和/或写入光学存储介质的方法，软件和装置。 所述方法通常包括用于读取光学存储介质的区域以产生回读信号的步骤，处理预定图案数据以产生一个或多个测量指令，响应于测量指令测量回读信号的一个或多个特性以产生一个 或更多的测量结果，并且根据测量结果中的一个或多个进一步处理回读信号。 因此，提供了灵活地设置测试参数并且快速且准确地测试可记录或可重写光学存储介质的写入特性的能力。
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公开(公告)号：US06594716B2
公开(公告)日：2003-07-15
申请号：US09892489
申请日：2001-06-28
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F1312
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.
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公开(公告)号：US08060674B2
公开(公告)日：2011-11-15
申请号：US12435945
申请日：2009-05-05
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F13/00
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.
摘要翻译： 集成数据存储控制系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其它以前分立的组件，在一个高度集成的系统设计中。 使用针对所有组件的单个集成电路技术类型（例如，数字CMOS）来呈现集成电路。 模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。 单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。 本发明可以应用于磁性硬盘驱动器（HDD）或诸如软盘控制器，光盘驱动器（例如CD-ROM等），磁带驱动器和其他数据存储设备的其它类型的存储设备。
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10.发明授权Mixed-signal single-chip integrated system electronics for magnetic hard disk drives 有权用于磁性硬盘驱动器的混合信号单芯片集成系统电子设备公开(公告)号：US06314480B1
公开(公告)日：2001-11-06
申请号：US09435719
申请日：1999-11-08
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F1300
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated HDD system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g. digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. The invention takes advantage of existing circuit design modules provided in the integrated circuit as “hard block” components which are unchanged by integrated circuit design software. Changes in operability of the overall integrated circuit may be readily achieved by altering “soft block” components to customize or tailor the design for a particular hard drive. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components.
摘要翻译： 集成式HDD系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其他以前分立组件的高度集成的系统设计。 使用用于所有组件的单个集成电路技术类型（例如数字CMOS）来呈现集成电路。 模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。 本发明利用集成电路中提供的现有电路设计模块作为集成电路设计软件不变的“硬块”组件。 通过改变“软块”组件来定制或定制特定硬盘驱动器的设计可以容易地实现整个集成电路的可操作性的改变。 单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。
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