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    Compositions for use in security marking
    5.
    发明授权
    Compositions for use in security marking 有权

    公开(公告)号：US10472676B2

    公开(公告)日：2019-11-12

    申请号：US13265758

    申请日：2010-04-23

    申请人： Jason Brown ,  Bas Reichert

    发明人： Jason Brown ,  Bas Reichert

    IPC分类号： C12Q1/68 ,  C12Q1/6876 ,  C12Q1/6813

    摘要： A composition comprising: a plurality of identical first synthetic nucleotide oligomers; and a plurality of identical second synthetic nucleotide oligomers which are different to the first synthetic nucleotide oligomers, wherein each of the first synthetic nucleotide oligomers comprises a first primer binding sequence of bases, a first identifier sequence of three to seven bases in length, and a second primer binding sequence of bases, the first identifier sequence being disposed between the first and second primer binding sequences, wherein each of the second synthetic nucleotide oligomers comprises a third primer binding sequence of bases, a second identifier sequence of three to seven bases in length, and a fourth primer binding sequence of bases, the second identifier sequence being disposed between the third and fourth primer binding sequences, and wherein the first identifier sequence is different to the second identifier sequence.

    UICC control over devices used to obtain service
    7.
    发明授权
    UICC control over devices used to obtain service 有权
    UICC控制用于获取服务的设备

    公开(公告)号：US08639290B2

    公开(公告)日：2014-01-28

    申请号：US12567278

    申请日：2009-09-25

    申请人： Jason Brown ,  Inderpreet Singh Ahluwalia

    发明人： Jason Brown ,  Inderpreet Singh Ahluwalia

    IPC分类号： H04B1/38

    CPC分类号： H04M1/67 ,  H04M2250/14

    摘要： Devices and methods are disclosed by which a smart card or UICC that is removably insertable into a wireless terminal will only allow operation in either a specific terminal or a specific set of terminals. A mechanism to restrict the set of terminals that a UICC will operate with based upon logic embedded in a memory within the UICC. The UICC receives specific information from the wireless terminal when the terminal is turned on. If the information received satisfies a plurality of rules or conditions stored within the UICC, the UICC functions normally and the terminal may be registered with the network. If the UICC is inserted in an unsupported terminal, the UICC will refuse to function normally. This provides a deterrent against UICC theft.

    摘要翻译： 公开了可移除地插入到无线终端中的智能卡或UICC的设备和方法将仅允许在特定终端或特定终端集合中进行操作。 一种基于嵌入在UICC内的存储器中的逻辑来限制UICC将运行的终端集的机制。 当终端打开时，UICC从无线终端接收特定信息。 如果接收到的信息满足存储在UICC内的多个规则或条件，则UICC正常工作，终端可以向网络注册。 如果UICC插入不支持的终端，则UICC将拒绝正常运行。 这为UICC盗窃提供了威慑力。

    METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER
    8.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER 审中-公开
    高电压缓冲器的方法，器件和系统

    公开(公告)号：US20110298494A1

    公开(公告)日：2011-12-08

    申请号：US13210914

    申请日：2011-08-16

    申请人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    发明人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    IPC分类号： H03K19/094

    CPC分类号： H03K19/01721

    摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up pre-driver operably coupled to a primary pull-up transistor; a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor; a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. The pre-drivers may provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage and less than or equal to a supply voltage.

    摘要翻译： 公开了方法，装置和系统，包括用于具有向薄栅极介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括可操作地耦合到初级上拉晶体管的初级上拉预驱动器; 可操作地耦合到次级上拉晶体管的次级上拉预驱动器; 可操作地耦合到初级下拉晶体管的主下拉预驱动器; 以及可操作地耦合到次级下拉晶体管的次级下拉预驱动器。 预驱动器可以向可操作地耦合到其的晶体管的栅极提供足够低的电压，以便维持晶体管的栅极电介质完整性，其中初级上拉预驱动器，次级上拉电路中的至少一个 预驱动器，主下拉预驱动器和辅助下拉预驱动器被配置为提供大于或等于接地电压并小于或等于电源电压的电压。

    Methods, devices, and systems for a high voltage tolerant buffer
    9.
    发明授权
    Methods, devices, and systems for a high voltage tolerant buffer 有权
    用于高电压容限缓冲器的方法，设备和系统

    公开(公告)号：US08004313B2

    公开(公告)日：2011-08-23

    申请号：US12577506

    申请日：2009-10-12

    申请人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    发明人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/01721

    摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices.

    摘要翻译： 公开了方法，装置和系统，包括用于具有被配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括多个预驱动器，其中多个预驱动器中的每个预驱动器可操作地耦合到多个晶体管的晶体管。 缓冲器还可以包括一个或多个钳位装置，其中多个晶体管中的至少一个晶体管具有耦合到一个或多个钳位装置的至少一个夹持装置的栅极。

    Write command and write data timing circuit and methods for timing the same
    10.
    发明授权
    Write command and write data timing circuit and methods for timing the same 有权
    写命令和写数据定时电路和定时方法相同

    公开(公告)号：US07969813B2

    公开(公告)日：2011-06-28

    申请号：US12416761

    申请日：2009-04-01

    申请人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    发明人： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

    IPC分类号： G11C8/00

    CPC分类号： G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2272

    摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

    摘要翻译： 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。