公开(公告)号：US20220093763A1

公开(公告)日：2022-03-24

申请号：US17325214

申请日：2021-05-20

申请人： Winbond Electronics Corp.

发明人： Yi-Tsung Tsai ,  Chih-Hao Lin

IPC分类号： H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

摘要： Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.

公开(公告)号：US11245026B2

公开(公告)日：2022-02-08

申请号：US16692186

申请日：2019-11-22

申请人： Winbond Electronics Corp.

发明人： Yi-Tsung Tsai ,  Chia-Wei Wu ,  Chih-Hao Lin ,  Chien-Chih Li

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8234 ,  H01L21/8238

摘要： A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

公开(公告)号：US11729968B2

公开(公告)日：2023-08-15

申请号：US17375560

申请日：2021-07-14

申请人： Winbond Electronics Corp.

发明人： Chih-Hao Lin

IPC分类号： H10B12/00

CPC分类号： H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/485

摘要： A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.

公开(公告)号：US10741561B2

公开(公告)日：2020-08-11

申请号：US16565519

申请日：2019-09-10

申请人： Winbond Electronics Corp.

发明人： Chih-Hao Lin

IPC分类号： H01L27/10 ,  H01L29/66 ,  H01L27/108 ,  H01L21/768 ,  H01L23/58 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51

摘要： A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer.

公开(公告)号：US20180122809A1

公开(公告)日：2018-05-03

申请号：US15588713

申请日：2017-05-08

申请人： Winbond Electronics Corp.

发明人： Chih-Hao Lin

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L23/58 ,  H01L21/768 ,  H01L29/51 ,  H01L27/092

CPC分类号： H01L27/10814 ,  H01L21/76802 ,  H01L21/823842 ,  H01L23/585 ,  H01L27/092 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.

公开(公告)号：US11309433B2

公开(公告)日：2022-04-19

申请号：US16822030

申请日：2020-03-18

申请人： Winbond Electronics Corp.

发明人： Yi-Hui Chen ,  Chih-Hao Lin

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/49 ,  H01L21/764 ,  H01L29/51

摘要： A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

公开(公告)号：US11101272B2

公开(公告)日：2021-08-24

申请号：US16812065

申请日：2020-03-06

申请人： WINBOND ELECTRONICS CORP.

发明人： Chih-Hao Lin

IPC分类号： H01L27/108

摘要： A dynamic random access memory and its manufacturing method are provided. The memory includes a buried bit line, a plurality of buried word lines, a bit line contact structure, and a conductive plug. The buried bit line is formed in a substrate. A bottom surface of the buried word line is higher than a top surface of the buried bit line. The bit line contact structure is formed on the buried bit line and has a through hole. The bit line contact structure is not in direct contact with the buried bit line. A material of the bit line contact structure is different from a material of the buried bit line. The conductive plug is formed between the bit line contact structure and the buried bit line and fills the through hole, so that the bit line contact structure and the buried bit line are electrically connected.

公开(公告)号：US11705495B2

公开(公告)日：2023-07-18

申请号：US17325214

申请日：2021-05-20

申请人： Winbond Electronics Corp.

发明人： Yi-Tsung Tsai ,  Chih-Hao Lin

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H10B41/30

CPC分类号： H01L29/42324 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

摘要： Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.

公开(公告)号：US20210296486A1

公开(公告)日：2021-09-23

申请号：US16822030

申请日：2020-03-18

申请人： Winbond Electronics Corp.

发明人： Yi-Hui Chen ,  Chih-Hao Lin

IPC分类号： H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/764

摘要： A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

公开(公告)号：US10453848B2

公开(公告)日：2019-10-22

申请号：US15588713

申请日：2017-05-08

申请人： Winbond Electronics Corp.

发明人： Chih-Hao Lin

IPC分类号： H01L21/76 ,  H01L27/108 ,  H01L29/66 ,  H01L21/768 ,  H01L23/58 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

摘要： A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.