公开(公告)号：US09972626B1

公开(公告)日：2018-05-15

申请号：US15629758

申请日：2017-06-22

申请人： Winbond Electronics Corp.

发明人： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

IPC分类号： H01L27/108

CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

摘要： Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

公开(公告)号：US10818670B2

公开(公告)日：2020-10-27

申请号：US16542954

申请日：2019-08-16

申请人： Winbond Electronics Corp.

发明人： Jiun-Sheng Yang ,  Noriaki Ikeda

IPC分类号： H01L27/10 ,  H01L27/108

摘要： A memory device and a method for manufacturing the memory device are provided. The memory device includes an interlayer insulating layer formed on a substrate, a conductive contact plug formed in the interlayer insulating layer, a conductive barrier structure formed on the conductive contact plug, and a capacitor structure formed on the conductive barrier structure. The area of the top surface of the conductive contact plug is smaller than the area of the bottom surface of the conductive barrier structure, and the top surface of the conductive contact plug is completely covered by the bottom surface of the conductive barrier structure.

公开(公告)号：US10074654B1

公开(公告)日：2018-09-11

申请号：US15942439

申请日：2018-03-31

申请人： Winbond Electronics Corp.

发明人： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

IPC分类号： H01L27/108

CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

摘要： Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

公开(公告)号：US11217587B2

公开(公告)日：2022-01-04

申请号：US16431746

申请日：2019-06-05

申请人： Winbond Electronics Corp.

发明人： Noriaki Ikeda

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L23/31 ,  H01L21/311 ,  H01L21/3213

摘要： A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

公开(公告)号：US11139306B2

公开(公告)日：2021-10-05

申请号：US16424143

申请日：2019-05-28

申请人： WINBOND ELECTRONICS CORP.

发明人： Noriaki Ikeda

IPC分类号： H01L27/108

摘要： A memory device including a substrate, a non-doped semiconductor layer, a plurality of contact portions and a metal-stacking layer is provided. The substrate includes a plurality of word lines and a plurality of isolation structures. The non-doped semiconductor layer is disposed on the substrate. The contact portions are adjacent to the non-doped semiconductor layer and in direct contact with the substrate. The metal-stacking layer is disposed on the substrate. A portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and in direct contact with the contact portions.

公开(公告)号：US10043810B1

公开(公告)日：2018-08-07

申请号：US15680217

申请日：2017-08-18

申请人： Winbond Electronics Corp.

发明人： Noriaki Ikeda

IPC分类号： H01L29/49 ,  H01L27/108

摘要： A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a plurality of isolation structures, a plurality of word lines, a plurality of bit line contacts and a plurality of buried bit lines. The isolation structures are located in the substrate and defines a plurality of active regions extending along a first direction. The word lines are located in the substrate and are extending along a second direction, the second direction intersects with the first direction. The bit line contacts are located above the isolation structures, wherein each of the bit line contacts have a diffusion region that defines a bit line side contact. The buried bit lines are located above the bit line contacts and are connected to the active region via the bit line side contact, the buried bit lines are extending along the first direction and is parallel with the plurality of active regions.

公开(公告)号：US10714483B2

公开(公告)日：2020-07-14

申请号：US16183143

申请日：2018-11-07

申请人： Winbond Electronics Corp.

发明人： Huang-Nan Chen ,  Noriaki Ikeda

IPC分类号： H01L27/108

摘要： Memory devices include a first dielectric layer disposed on a substrate. Memory devices include a pair of contacts and a dielectric portion disposed in an opening of the first dielectric layer. The pair of contacts are separated from each other by the dielectric portion. Each contact includes a first conductive portion disposed on the substrate, a second conductive portion disposed over the first conductive portion and a lining layer disposed between the first conductive portion and the second conductive portion and on a sidewall of the opening. The second conductive portion has a sidewall that is in contact with the dielectric portion and the lining layer is not located thereon. The second conductive portion has a corner in connection with the sidewall and a top surface of the second conductive portion, and a protection portion is disposed on the corner.

公开(公告)号：US20220077153A1

公开(公告)日：2022-03-10

申请号：US17527117

申请日：2021-11-15

申请人： Winbond Electronics Corp.

发明人： Noriaki Ikeda

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L23/31 ,  H01L21/311 ,  H01L21/3213

摘要： A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

公开(公告)号：US11121135B1

公开(公告)日：2021-09-14

申请号：US16874680

申请日：2020-05-15

申请人： Winbond Electronics Corp.

发明人： Noriaki Ikeda

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L21/762 ,  H01L23/532 ,  H01L23/528 ,  H01L49/02

摘要： A structure of memory cell includes a substrate. The substrate includes a first active region, a second active region and a first shallow trench isolation (STI) structure between the first active region and the second active region, wherein the first active region is lower than the second active region. A first contact structure is disposed on the first active region. A first stack structure is on the first contact structure. A second contact structure is on the substrate with a bottom portion in the substrate at an interface between the second active region and the first STI structure. A dielectric spacer is at least on a sidewall of the first contact structure. An insulating layer is disposed on the dielectric spacer and between the second contact structure and the first contact structure with the first stack structure, wherein a dielectric constant of the dielectric spacer is lower than a dielectric constant of the insulating layer.

公开(公告)号：US11056175B1

公开(公告)日：2021-07-06

申请号：US16940411

申请日：2020-07-28

申请人： Winbond Electronics Corp.

发明人： Noriaki Ikeda

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06 ,  G11C11/24

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, word lines and bit lines. The semiconductor substrate has active regions separated from one another and extending along a first direction. The word lines are formed in the semiconductor substrate. The active regions are respectively intersected with one or more of the word lines. The word lines respectively have thick portions and a narrow portion continuously extending on the thick portions along a second direction. The thick portions are located at where the word lines are intersected with the active regions. The bit lines are formed over the semiconductor substrate, and extending along a third direction intersected with the first and second directions.