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公开(公告)号：US11793095B2
公开(公告)日：2023-10-17
申请号：US17392268
申请日：2021-08-03
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Shih-Ning Tsai , Tse-Mian Kuo
CPC classification number: H10N70/841 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/24 , H10N70/826 , H10N70/8833
Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
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公开(公告)号：US11495637B2
公开(公告)日：2022-11-08
申请号：US16919047
申请日：2020-07-01
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Shih-Ning Tsai , Bo-Lun Wu , Tse-Mian Kuo
Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
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公开(公告)号：US11177321B2
公开(公告)日：2021-11-16
申请号：US16661121
申请日：2019-10-23
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Shih-Ning Tsai , Cheng-Hui Tu
Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and located on one side of the first electrode, a first metal oxide layer formed on sidewalls of the second electrode, a first control layer formed between the first electrode and the first metal oxide layer, and a second control layer formed on the first control layer and located between the first electrode and the first metal oxide layer.
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Patent Agency Ranking
公开(公告)号：US20220093858A1
公开(公告)日：2022-03-24
申请号：US17027700
申请日：2020-09-21
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Shih-Ning Tsai
Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
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公开(公告)号：US20220005868A1
公开(公告)日：2022-01-06
申请号：US16919047
申请日：2020-07-01
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Shih-Ning Tsai , Bo-Lun Wu , Tse-Mian Kuo
Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
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公开(公告)号：US11770985B2
公开(公告)日：2023-09-26
申请号：US17027700
申请日：2020-09-21
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Shih-Ning Tsai
CPC classification number: H10N70/841 , H10B63/00 , H10N70/063 , H10N70/24 , H10N70/8833
Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
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公开(公告)号：US20220216401A1
公开(公告)日：2022-07-07
申请号：US17392268
申请日：2021-08-03
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Shih-Ning Tsai , Tse-Mian Kuo
Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
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公开(公告)号：US11011702B2
公开(公告)日：2021-05-18
申请号：US16534608
申请日：2019-08-07
Applicant: Winbond Electronics Corp.
Inventor： Bo-Lun Wu , Shih-Ning Tsai , Po-Yen Hsu
IPC: H01L45/00
Abstract: A memory device includes a first electrode, a resistive switching layer, a cap layer, a protective layer, and a second electrode. The resistive switching layer is disposed over the first electrode. The cap layer is disposed over the resistive switching layer, wherein the bottom surface of the cap layer is smaller than the top surface of the resistive switching layer. The protective layer is disposed over the resistive switching layer and surrounds the cap layer. At least a portion of the second electrode is disposed over the cap layer and covers the protective layer.
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