公开(公告)号：US11770985B2

公开(公告)日：2023-09-26

申请号：US17027700

申请日：2020-09-21

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Shih-Ning Tsai

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/00 ,  H10N70/063 ,  H10N70/24 ,  H10N70/8833

Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.

公开(公告)号：US11601267B2

公开(公告)日：2023-03-07

申请号：US16361796

申请日：2019-03-22

Applicant: Winbond Electronics Corp.

Inventor： Meng-Hung Lin ,  Chia Hua Ho ,  Bo-Lun Wu

IPC: H04L9/08 ,  G11C13/00

Abstract: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.

公开(公告)号：US20220216401A1

公开(公告)日：2022-07-07

申请号：US17392268

申请日：2021-08-03

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Shih-Ning Tsai ,  Tse-Mian Kuo

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.

公开(公告)号：US11329222B2

公开(公告)日：2022-05-10

申请号：US16839270

申请日：2020-04-03

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Ting-Ying Shen

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.

公开(公告)号：US11011702B2

公开(公告)日：2021-05-18

申请号：US16534608

申请日：2019-08-07

Applicant: Winbond Electronics Corp.

Inventor： Bo-Lun Wu ,  Shih-Ning Tsai ,  Po-Yen Hsu

IPC: H01L45/00

Abstract: A memory device includes a first electrode, a resistive switching layer, a cap layer, a protective layer, and a second electrode. The resistive switching layer is disposed over the first electrode. The cap layer is disposed over the resistive switching layer, wherein the bottom surface of the cap layer is smaller than the top surface of the resistive switching layer. The protective layer is disposed over the resistive switching layer and surrounds the cap layer. At least a portion of the second electrode is disposed over the cap layer and covers the protective layer.

公开(公告)号：US09166160B1

公开(公告)日：2015-10-20

申请号：US14481925

申请日：2014-09-10

Applicant: Winbond Electronics Corp.

Inventor： Chia-Hua Ho ,  Shuo-Che Chang ,  Hsiu-Han Liao ,  Po-Yen Hsu ,  Meng-Hung Lin ,  Bo-Lun Wu ,  Ting-Ying Shen

IPC: H01L47/00 ,  H01L21/20 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.

Abstract translation: 本发明提供一种电阻随机存取存储器，包括第一电极层，第二电极层和设置在第一电极层和第二电极层之间的可变电阻层，其中第二电极层包括第一子层，第二子层和 设置在第一子层和第二子层之间的导电金属氮氧化物层。

公开(公告)号：US12114579B2

公开(公告)日：2024-10-08

申请号：US18463268

申请日：2023-09-07

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Tse-Mian Kuo

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/021 ,  H10B63/84 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841 ,  H10N70/8833

Abstract: A method of fabricating a resistive random access memory cell includes the following steps. A second sacrificial layer is formed around a patterned stacked layer. An opening passing through first conductive layers and first sacrificial layers of the patterned stacked layer is formed. A second conductive layer is formed in the opening, and the second conductive layer and the first conductive layers form a first electrode layer. The first sacrificial layers and the second sacrificial layer are removed. A variable resistance layer and an oxygen reservoir layer are formed. The oxygen reservoir layer is patterned to form a patterned oxygen reservoir layer and expose the variable resistance layer. A second dielectric layer is formed on the variable resistance layer and the patterned oxygen reservoir layer. A second electrode is formed in the second dielectric layer.

公开(公告)号：US11552245B2

公开(公告)日：2023-01-10

申请号：US16803351

申请日：2020-02-27

Applicant: Winbond Electronics Corp.

Inventor： Chih-Yao Lin ,  Po-Yen Hsu ,  Bo-Lun Wu

IPC: H01L45/00 ,  H01L27/24

Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.

公开(公告)号：US11495637B2

公开(公告)日：2022-11-08

申请号：US16919047

申请日：2020-07-01

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Shih-Ning Tsai ,  Bo-Lun Wu ,  Tse-Mian Kuo

IPC: H01L27/24 ,  G11C7/18 ,  H01L45/00

Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.

公开(公告)号：US20220093859A1

公开(公告)日：2022-03-24

申请号：US17543732

申请日：2021-12-07

Applicant: Winbond Electronics Corp.

Inventor： Bo-Lun Wu ,  Po-Yen Hsu

IPC: H01L45/00

Abstract: Provided is a method of manufacturing a resistive random access memory (RRAM) including: forming a lower electrode protruding from a top surface of a dielectric layer; conformally forming a data storage layer on the lower electrode and the dielectric layer; forming an oxygen reservoir material layer on the data storage layer; forming an opening in the oxygen reservoir material layer to expose the data storage layer on the lower electrode; forming an isolation structure in the opening, wherein the isolation structure divides the oxygen reservoir material layer into a first oxygen reservoir layer and a second oxygen reservoir layer; and forming an upper electrode on the first and second oxygen reservoir layers, wherein the first and second oxygen reservoir layers share the upper electrode.