公开(公告)号：US09373391B1

公开(公告)日：2016-06-21

申请号：US14850974

申请日：2015-09-11

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Wen-Hsiung Chang ,  Chien-Min Wu

IPC: G11C13/00 ,  G11C5/06

CPC classification number: G11C13/0002 ,  G11C5/06 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463

Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.

Abstract translation: 提供了一种电阻式存储装置。 电阻式存储装置包括多个存储单元对，并且每个存储单元对包括有源区，第一和第二字线，源极线，第一和第二电阻以及第一和第二位线。 有源区形成在基板上，第一和第二字线形成在基板上，并与有源区相交。 源极线形成在衬底上并耦合到有源区。 第一和第二电阻器设置在基板上，并且分别耦合到有源区域。 第一和第二位线形成在第一和第二电阻上并耦合到第一和第二电阻器。 第一和第二位线沿着基本上平行于第一和第二字线的第一方向延伸。