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公开(公告)号：US11785869B2
公开(公告)日：2023-10-10
申请号：US17344963
申请日：2021-06-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
CPC classification number: H10N70/8265 , H10B63/845 , H10N70/011
Abstract: Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.
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公开(公告)号：US11289157B1
公开(公告)日：2022-03-29
申请号：US17012077
申请日：2020-09-04
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Kuang-Chih Hsieh , Chien-Min Wu , Meng-Hung Lin
Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.
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公开(公告)号：US11055021B2
公开(公告)日：2021-07-06
申请号：US16353339
申请日：2019-03-14
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.
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公开(公告)号：US10121826B1
公开(公告)日：2018-11-06
申请号：US15499904
申请日：2017-04-28
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: H01L29/06 , H01L27/24 , H01L45/00 , H01L29/78 , H01L29/423 , H01L27/22 , H01L43/02 , G11C11/16 , H01L43/08 , H01L23/528 , H01L43/12
Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.
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公开(公告)号：US20180315795A1
公开(公告)日：2018-11-01
申请号：US15499904
申请日：2017-04-28
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: H01L27/24 , H01L45/00 , H01L29/78 , H01L29/423 , H01L27/22 , H01L43/02 , G11C11/16 , H01L43/08 , H01L23/528 , H01L29/06 , H01L43/12
Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.
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Patent Agency Ranking
公开(公告)号：US10103325B2
公开(公告)日：2018-10-16
申请号：US15379505
申请日：2016-12-15
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: H01L45/00 , H01L47/00 , H01L21/3205 , G11C13/00 , G11C11/00
Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
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公开(公告)号：US20160372196A1
公开(公告)日：2016-12-22
申请号：US15088138
申请日：2016-04-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.
Abstract translation: 提供了一种用于电阻式存储装置的写入方法。 在该方法中，接收逻辑数据，并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。
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公开(公告)号：US09508435B1
公开(公告)日：2016-11-29
申请号：US15088138
申请日：2016-04-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.
Abstract translation: 提供了一种用于电阻式存储装置的写入方法。 在该方法中，接收逻辑数据，并且选择对应的选择存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供小于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。 当逻辑数据处于第二逻辑电平时，将RESET脉冲提供给选择存储单元，然后在写入期间向选择存储单元提供大于参考写入电流且具有近矩形脉冲宽度的SET脉冲 期。
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公开(公告)号：US12185553B2
公开(公告)日：2024-12-31
申请号：US17715065
申请日：2022-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Chih-Chao Huang , Ming-Che Lin , Frederick Chen , Han-Huei Hsu
Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
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公开(公告)号：US12040218B2
公开(公告)日：2024-07-16
申请号：US17371605
申请日：2021-07-09
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: H01L21/76 , H01L21/033 , H01L21/762 , H10B12/00
CPC classification number: H01L21/76224 , H01L21/0337 , H10B12/0335 , H10B12/0387 , H10B12/31 , H10B12/34
Abstract: A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.
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