公开(公告)号：US06243781B1

公开(公告)日：2001-06-05

申请号：US09205051

申请日：1998-12-03

申请人： Wishwesh Gandhi ,  Tuong Trieu ,  Ashish Gadagkar ,  Zohar Bogin ,  David D. Lent

发明人： Wishwesh Gandhi ,  Tuong Trieu ,  Ashish Gadagkar ,  Zohar Bogin ,  David D. Lent

IPC分类号： G06F1314

CPC分类号： G06F13/4036

摘要： In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.

摘要翻译： 在具有用于以FIFO方式处理非发布和发布的交易的出站管道的总线资源中，在出站管道的头部处的被拒绝的非贴现事务被移动到辅助缓冲器中，以避免潜在的阻塞 出站管道 辅助缓冲区用于保存交易信息并返回被拒绝的非贴现交易的数据。 被拒绝的事务最终由仲裁器确定的辅助缓冲区完成。

公开(公告)号：US20090172676A1

公开(公告)日：2009-07-02

申请号：US12006243

申请日：2007-12-31

申请人： Hong Jiang ,  Wishwesh Gandhi

发明人： Hong Jiang ,  Wishwesh Gandhi

IPC分类号： G06F9/46

CPC分类号： G06F9/4843

摘要： A batch computer or batch processor may implement conditional execution at the command level of the batch processor or higher. Conditional execution may involve execution of one batch buffer depending on the results achieved upon execution by another batch buffer.

摘要翻译： 批处理计算机或批处理器可以在批处理器的命令级别或更高级别执行条件执行。 有条件执行可能涉及一个批处理缓冲区的执行，这取决于另一个批处理缓冲区执行时取得的结果。

公开(公告)号：US20130298124A1

公开(公告)日：2013-11-07

申请号：US13932963

申请日：2013-07-01

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC分类号： G06F9/455

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

摘要翻译： 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。

公开(公告)号：US08154555B2

公开(公告)日：2012-04-10

申请号：US12912630

申请日：2010-10-26

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC分类号： G09G5/39 ,  G06F13/00 ,  G06F12/10

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

摘要翻译： 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。

公开(公告)号：US06629217B1

公开(公告)日：2003-09-30

申请号：US09469653

申请日：1999-12-22

申请人： Steve J. Clohset ,  Tuong P. Trieu ,  Wishwesh Gandhi

发明人： Steve J. Clohset ,  Tuong P. Trieu ,  Wishwesh Gandhi

IPC分类号： G06F1216

CPC分类号： G06F13/161

摘要： A method and apparatus for improving read latency for processor to system memory read transactions is disclosed. One embodiment of a system logic device includes logic that assumes a transfer size of a predetermined length. In this manner, the system logic device can issue a read transaction request to system memory as soon as the read request address is delivered by the processor rather than waiting for the processor to deliver information indicating the transfer length. Once the actual transfer length information is delivered from the processor to the system logic device, the system logic device determines whether any of the data returned by the system memory needs to be purged before returning the requested data to the processor.

摘要翻译： 公开了一种用于改善处理器到系统存储器读取事务的读延迟的方法和装置。 系统逻辑设备的一个实施例包括假定具有预定长度的传送大小的逻辑。 以这种方式，一旦读请求地址由处理器传送，系统逻辑设备就可以向系统存储器发出读取事务请求，而不是等待处理器传递指示传送长度的信息。 一旦将实际的传输长度信息从处理器传送到系统逻辑设备，则系统逻辑设备确定在将所请求的数据返回给处理器之前需要清除由系统存储器返回的任何数据。

公开(公告)号：US06560657B1

公开(公告)日：2003-05-06

申请号：US09470705

申请日：1999-12-23

申请人： Wishwesh Gandhi ,  Aditya Sreenivas ,  Peter Doyle

发明人： Wishwesh Gandhi ,  Aditya Sreenivas ,  Peter Doyle

IPC分类号： G06F1310

CPC分类号： G06F13/126

摘要： A system and method for controlling peripheral devices wherein at least one command is written to a location in a system memory and a write pointer is advanced. A peripheral device then reads the at least one command from that location in memory, increments a read pointer and executes the at least one command.

摘要翻译： 一种用于控制外围设备的系统和方法，其中至少一个命令被写入系统存储器中的位置并且写指针被提前。 然后，外围设备从存储器中的该位置读取至少一个命令，增加读指针并执行至少一个命令。

公开(公告)号：US08522242B2

公开(公告)日：2013-08-27

申请号：US12006243

申请日：2007-12-31

申请人： Hong Jiang ,  Wishwesh Gandhi

发明人： Hong Jiang ,  Wishwesh Gandhi

IPC分类号： G06F9/46

CPC分类号： G06F9/4843

摘要： A batch computer or batch processor may implement conditional execution at the command level of the batch processor or higher. Conditional execution may involve execution of one batch buffer depending on the results achieved upon execution by another batch buffer.

公开(公告)号：US08477145B2

公开(公告)日：2013-07-02

申请号：US13369720

申请日：2012-02-09

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC分类号： G06F12/10 ,  G06F12/06 ,  G09G5/39

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

公开(公告)号：US20090172331A1

公开(公告)日：2009-07-02

申请号：US12006282

申请日：2007-12-31

申请人： Balaji Vembu ,  Aditya Sreenivas ,  Wishwesh Gandhi ,  Sathyamurthi Sadhasivan ,  Gary Graunke ,  Scott Janus ,  Murali Ramadoss

发明人： Balaji Vembu ,  Aditya Sreenivas ,  Wishwesh Gandhi ,  Sathyamurthi Sadhasivan ,  Gary Graunke ,  Scott Janus ,  Murali Ramadoss

IPC分类号： G06F21/00

CPC分类号： G06F21/84 ,  G06F21/10 ,  G06F21/74

摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.

摘要翻译： 图形引擎可以包括全部连接到显示器的解密设备，渲染器和子画面或覆盖引擎。 在一个实施例中，存储器可以具有受保护和非保护部分。 应用可以将加密的内容存储在所述存储器的非保护部分上。 解密设备可以访问加密的材料，解密材料，并将其提供给图形引擎的渲染器引擎。 然后，图形引擎可以使用存储器的受保护部分来处理解密的材料。 只有图形设备才能以至少一种模式访问存储器的受保护部分，从而防止外部源的访问。 此外，受保护的存储器可能是未被识别到操作系统的被盗存储器，使得被盗的存储器不能在操作系统上运行的应用程序访问。