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    Avoiding livelock when performing a long stream of transactions
    2.
    发明授权
    Avoiding livelock when performing a long stream of transactions 失效
    执行长时间的事务时避免活动锁定

    公开(公告)号：US06237055B1

    公开(公告)日：2001-05-22

    申请号：US09205024

    申请日：1998-12-03

    申请人： Tuong Trieu ,  David D. Lent ,  Zohar Bogin ,  Ashish Gadagkar

    发明人： Tuong Trieu ,  David D. Lent ,  Zohar Bogin ,  Ashish Gadagkar

    IPC分类号： G06F13362

    CPC分类号： G06F13/364

    摘要： An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.

    摘要翻译： 一种仲裁器，包括逻辑电路，其被配置为响应于接收到指示耦合到总线的设备不能用于通过总线对设备进行服务的事务的第一信号来延迟向代理X授予总线所有权。 例如，如果桥的入站管道已满，则设备可能是桥接器，并且延迟许可。 仲裁器可以向设备的出站管道提供借用的授权，用于在等待设备的入站管道变得可用时在总线上进行交易。

    Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge
    3.
    发明授权
    Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge 有权
    仲裁方法，以避免跨越桥梁进行交易时的僵局和活锁

    公开(公告)号：US06202112B1

    公开(公告)日：2001-03-13

    申请号：US09205351

    申请日：1998-12-03

    申请人： Ashish Gadagkar ,  Zohar Bogin ,  Narendra Khandekar ,  David D. Lent

    发明人： Ashish Gadagkar ,  Zohar Bogin ,  Narendra Khandekar ,  David D. Lent

    IPC分类号： G06F1342

    CPC分类号： G06F13/4036

    摘要： An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.

    摘要翻译： 本发明的一个实施例涉及一种具有用于缓冲交易信息和从各种设备传输到总线的数据的出站管的桥。 桥接器具有用于授予与这些设备相关联的请求的仲裁器以访问出站管道，用于将事务信息和数据传送到管道中。 如果出站管道不可用于接受进一步的交易信息或数据，则桥接器响应于与来自第一设备的初始事务相关联的初始请求生成拒绝信号。 桥接器具有用于响应于拒绝信号而产生用于初始事务的重试响应的响应控制逻辑。 桥接器能够响应于拒绝信号来声明印记信号。 响应于该邮票被断言的仲裁者等待，而不允许任何其他较低优先级的请求访问出站管道，直到来自第一个设备的后续事务进行。

    Deterministic shut down of memory devices in response to a system warm reset
    5.
    发明授权
    Deterministic shut down of memory devices in response to a system warm reset 有权
    响应于系统热复位，确定性地关闭存储器件

    公开(公告)号：US07181605B2

    公开(公告)日：2007-02-20

    申请号：US10693226

    申请日：2003-10-24

    申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    IPC分类号： G06F9/00

    CPC分类号： G06F1/24

    摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

    摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

    Apparatus and method for open loop buffer allocation
    8.
    发明申请
    Apparatus and method for open loop buffer allocation 审中-公开
    开环缓冲区分配的装置和方法

    公开(公告)号：US20050198459A1

    公开(公告)日：2005-09-08

    申请号：US10795037

    申请日：2004-03-04

    申请人： Zohar Bogin ,  Tuong Trieu ,  Sarath Kotamreddy ,  Jayesh Laddha

    发明人： Zohar Bogin ,  Tuong Trieu ,  Sarath Kotamreddy ,  Jayesh Laddha

    IPC分类号： G06F12/00

    CPC分类号： G06F5/06

    摘要： A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the load rate exceeds the drain rate, read requests may be throttled according to an approximate buffer capacity level to prohibit buffer overflow. In one embodiment, a rate for issuing data requests, for example, to memory, is regulated according to a predetermined buffer accumulation rate. Accordingly, in one embodiment, the open loop allocation scheme reduces latency while enabling sustained read streaming with a minimal size read buffer. Other embodiments are described and claimed.

    摘要翻译： 一种用于开环缓冲区分配的方法和装置。 在一个实施例中，该方法包括根据负载速率在缓冲器中加载所请求的数据。 与缓冲区内的数据加载一起，数据根据流失速率从缓冲区转发。 在负载率超过排放速率的情况下，读取请求可能会根据大约缓冲区容量限制，以禁止缓冲区溢出。 在一个实施例中，根据预定的缓冲器累积速率来调节用于发布数据请求（例如，存储器）的速率。 因此，在一个实施例中，开环分配方案减少等待时间，同时以最小尺寸的读缓冲器实现持续的读取流。 描述和要求保护其他实施例。

    Apparatus and a method to adjust signal timing on a memory interface
    9.
    发明申请
    Apparatus and a method to adjust signal timing on a memory interface 审中-公开
    用于调整存储器接口上的信号定时的装置和方法

    公开(公告)号：US20050190193A1

    公开(公告)日：2005-09-01

    申请号：US10791180

    申请日：2004-03-01

    申请人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    发明人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/372

    CPC分类号： G06F13/1689

    摘要： An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.

    摘要翻译： 已经公开了一种用于调整存储器接口中的信号定时的装置和方法。 该装置的一个实施例包括在存储器接口中的多个从属延迟锁定环（DLL），用于调整多个信号之间的定时以补偿定时偏差，以及多个输入/输出（I / O）缓冲器，以输出 调整的信号到耦合到存储器接口的一个或多个存储器件。 描述和要求保护其他实施例。