公开(公告)号：US07793345B2

公开(公告)日：2010-09-07

申请号：US11237038

申请日：2005-09-27

申请人： Wolf-Dietrich Weber ,  Drew E. Wingard ,  Stephen W. Hamilton ,  Frank Seigneret

发明人： Wolf-Dietrich Weber ,  Drew E. Wingard ,  Stephen W. Hamilton ,  Frank Seigneret

IPC分类号： G06F7/04 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F17/30 ,  G06F11/00 ,  G06F12/04 ,  G06F12/16 ,  G11C7/00 ,  G08B23/00

CPC分类号： G06F21/78 ,  G06F12/10 ,  Y02D10/13

摘要： Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.

摘要翻译： 描述了各种保护机制的方法和装置。 目标知识产权块可以在芯片上系统网络中来自发起者知识产权块的请求。 目标知识产权块具有相关联的保护机制，其逻辑被配置为将请求的访问限制到目标知识产权块。 基于与目标知识产权块内的区域相关联的访问权限和尝试访问该区域的请求的属性，请求的访问受到限制。

公开(公告)号：US20100057400A1

公开(公告)日：2010-03-04

申请号：US12204156

申请日：2008-09-04

申请人： Chien-Chun Chou ,  Stephen W. Hamilton ,  Drew E. Wingard ,  Pascal Chauvet

发明人： Chien-Chun Chou ,  Stephen W. Hamilton ,  Drew E. Wingard ,  Pascal Chauvet

IPC分类号： G21C17/00

CPC分类号： G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.

摘要翻译： 描述了提供电子设计的仪器和分析的各种方法和装置。 性能监视装置可以位于所制造的集成电路的互连上。 事件测量模块（EM）包括一个事件发生器子模块，该事件发生器子模块通过互连产生与发起者知识产权（IP）核心和目标IP内核之间的事务相关联的监视事件和事件测量。 EM还包括软件可见寄存器块，其提供用于控制EM监视的一个或多个事务的软件访问以及配置与该事务相关联的一个或多个参数以进行跟踪。 EM还包括一个过滤子模块，该过滤子模块根据从软件接收的信息来选择要监视的事务。 性能计数器模块将从EM接收到的事件和事件测量聚合到与互连上的IP内核之间的事务相关联的性能度量数量。

公开(公告)号：US20080320476A1

公开(公告)日：2008-12-25

申请号：US12144987

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F9/46

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。 集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。 互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。 在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前 同时确保在第一事务和第二事务期间的预期执行顺序。 该逻辑不包括任何重新排序缓冲。

公开(公告)号：US20130073878A1

公开(公告)日：2013-03-21

申请号：US13434605

申请日：2012-03-29

申请人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

发明人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

摘要翻译： 互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。 互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态 域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

公开(公告)号：US09292436B2

公开(公告)日：2016-03-22

申请号：US12145052

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F12/06 ,  G06F15/173

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。 两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。 第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

公开(公告)号：US20080320268A1

公开(公告)日：2008-12-25

申请号：US12144883

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Ian Andrew Swarbrick ,  Stephen W. Hamilton ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Ian Andrew Swarbrick ,  Stephen W. Hamilton ,  Vida Vakilotojar

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

摘要翻译： 在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。 两个或多个内存通道组成目标IP内核的第一个聚合目标。 两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务 ，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。

公开(公告)号：US20080320254A1

公开(公告)日：2008-12-25

申请号：US12145052

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F12/06

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。 两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。 第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

公开(公告)号：US09495290B2

公开(公告)日：2016-11-15

申请号：US12144987

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F9/46 ,  G06F9/455 ,  G06F12/06 ,  G06F15/173

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。 集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。 互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。 在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前 同时确保在第一事务和第二事务期间的预期执行顺序。 该逻辑不包括任何重新排序缓冲。

公开(公告)号：US08868941B2

公开(公告)日：2014-10-21

申请号：US13434605

申请日：2012-03-29

申请人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

发明人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06G7/54 ,  G06F13/00 ,  G06F15/00

CPC分类号： G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

摘要翻译： 互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。 互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态 域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

公开(公告)号：US08407433B2

公开(公告)日：2013-03-26

申请号：US12144883

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

摘要翻译： 在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。 两个或多个内存通道组成目标IP内核的第一个聚合目标。 两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务 ，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。