公开(公告)号：US06570794B1

公开(公告)日：2003-05-27

申请号：US10034626

申请日：2001-12-27

申请人： Wolfgang Hokenmaier ,  Gunther Lehmann ,  Gerd Frankowsky ,  David R. Hanson

发明人： Wolfgang Hokenmaier ,  Gunther Lehmann ,  Gerd Frankowsky ,  David R. Hanson

IPC分类号： G11C700

CPC分类号： G11C7/18 ,  G11C11/4097 ,  G11C29/70

摘要： A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

摘要翻译： 提供具有存储器单元的行和列阵列的存储器。 存储器包括多个读出放大器，每个读出放大器具有真正的终端和补码终端。 存储器还包括多对扭绞位线，每对线对中的每一对被耦合到多个读出放大器中对应的一个读出放大器的真实和补充端子。 提供多个字线，每个字线连接到存储器单元的行中相应的一行。 地址逻辑部分由馈送到位线的列地址信号和馈送到字线的行地址信号馈送，用于根据馈送的行和列地址信号产生反相/非反相信号。 存储器包括多个反相器，每个反相器被耦合到读出放大器中的对应的一个，用于根据由地址逻辑产生的反相/非反相信号选择性地反转馈送到读出放大器或从读出放大器读取的数据。

公开(公告)号：US06603694B1

公开(公告)日：2003-08-05

申请号：US10068789

申请日：2002-02-05

申请人： Gerd Frankowsky ,  Gunther Lehmann

发明人： Gerd Frankowsky ,  Gunther Lehmann

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.

摘要翻译： 提供了用于刷新存储在动态存储单元阵列中的数据的电路。 该电路包括集成电路芯片。 芯片具有形成在其上的存储单元阵列。 该电路还包括用于确定每个存储器单元中的数据保持时间的刷新率分析电路，以及这些确定刷新地址修改信号。 还提供了一种刷新地址生成器，其形成在芯片上并由芯片外部产生的刷新命令信号和地址修改信号馈送。 刷新地址生成器向内存单元阵列提供内部刷新命令以及刷新地址。 小区具有响应于这种内部刷新命令刷新的数据。 刷新率分析电路确定具有小于预定值的数据保留时间的阵列中的单元。

公开(公告)号：US06909642B2

公开(公告)日：2005-06-21

申请号：US10387435

申请日：2003-03-14

申请人： Gunther Lehmann ,  Gerd Frankowsky

发明人： Gunther Lehmann ,  Gerd Frankowsky

IPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C29/02 ,  G11C7/00

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/5004

摘要： Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

摘要翻译： 描述了能够自调整集成电路芯片的内部电压的集成电路芯片以及用于调整集成电路芯片的内部电压的方法。 这些方法包括将内部产生的电压与外部目标电压进行比较。

公开(公告)号：US06426911B1

公开(公告)日：2002-07-30

申请号：US09691953

申请日：2000-10-19

申请人： Gunther Lehmann ,  Gabriel Daniel ,  Gerd Frankowsky

发明人： Gunther Lehmann ,  Gabriel Daniel ,  Gerd Frankowsky

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

摘要翻译： 根据本发明的用于编程电熔丝的电路包括一个包括多个锁存器的移位寄存器。 每个闩锁都有相应的开关和相应的电保险丝。 位发生器产生第一状态的单个位和第二状态的所有其他位。 位产生器根据时钟信号将生成的比特传播到移位寄存器。 每个开关根据存储在相应的锁存器中的产生的位使能通过相应的电熔丝的导通。 吹电压线路连接到电气保险丝。 根据编程数据激活吹制电压线，以便根据编程数据来熔断熔丝，使得当第一状态的单个位被存储在对应于要编程的熔丝的锁存器中时，根据编程数据编程电熔丝。

公开(公告)号：US20050024090A1

公开(公告)日：2005-02-03

申请号：US10631394

申请日：2003-07-31

申请人： Hartmud Terletzki ,  Gerd Frankowsky ,  Gunther Lehmann

发明人： Hartmud Terletzki ,  Gerd Frankowsky ,  Gunther Lehmann

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K17/163 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018585

摘要： A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

摘要翻译： 提供了一种系统和方法，用于控制芯片外驱动电路的阻抗和电流，以匹配由驱动器驱动的负载，并减少芯片外驱动电路中的噪声和振铃。 驱动器包括用于将驱动器的输出切换到高电压的上拉晶体管，用于将驱动器的输出切换到低电压的下拉晶体管，耦合到上拉晶体管的第一电流镜晶体管，用于控制 当驱动器的输出处于高电压时，电流传输到连接到驱动器的负载;以及耦合到下拉晶体管的第二电流镜晶体管，用于当驱动器的输出处于该状态时控制传输到负载的电流 低电压。 此外，驱动器可以包括为具有受控转换速率的上拉晶体管提供栅极信号的第一预驱动器，以及为具有受控转换速率的下拉晶体管提供栅极信号的第二预驱动器。

公开(公告)号：US06608783B2

公开(公告)日：2003-08-19

申请号：US10034625

申请日：2001-12-27

申请人： Gerd Frankowsky ,  Gunther Lehmann ,  Hartmud Terletzki

发明人： Gerd Frankowsky ,  Gunther Lehmann ,  Hartmud Terletzki

IPC分类号： G11C700

CPC分类号： G11C11/4096 ,  G11C7/1006 ,  G11C7/18 ,  G11C11/4097

摘要： A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

摘要翻译： 提供具有存储器单元的行和列阵列的存储器。 存储器包括多个读出放大器，每个读出放大器具有真正的终端和补码终端。 存储器还包括多对扭绞位线，每对线对中的每一对被耦合到多个读出放大器中对应的一个读出放大器的真实和补充端子。 提供多个字线，每个字线连接到存储器单元的行中相应的一行。 地址逻辑部分由馈送到位线的列地址信号和馈送到字线的行地址信号馈送，用于根据馈送的行和列地址信号产生反相/非反相信号。 存储器包括多个反相器，每个反相器被耦合到读出放大器中的对应的一个，用于根据由地址逻辑产生的反相/非反相信号选择性地反转馈送到读出放大器或从读出放大器读取的数据。

公开(公告)号：US06601205B1

公开(公告)日：2003-07-29

申请号：US09675953

申请日：2000-09-29

申请人： Gunther Lehmann ,  Gerd Frankowsky ,  Louis Hsu ,  Armin Reith

发明人： Gunther Lehmann ,  Gerd Frankowsky ,  Louis Hsu ,  Armin Reith

IPC分类号： G01R3128

CPC分类号： G01R31/318378 ,  G01R31/3183 ,  G01R31/31926 ,  G11C29/10 ,  G11C29/56

摘要： An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.

摘要翻译： 用于在存储器电路中产生逻辑硬件测试图案的自动方法基于给定的物理模式。 该方法包括从给定的一组逻辑数据模式的向后变换。 由于该方法是自动的，所以不需要存储电路内的数据加扰知识。

公开(公告)号：US06809972B2

公开(公告)日：2004-10-26

申请号：US10387993

申请日：2003-03-13

申请人： Gunther Lehmann ,  Gerd Frankowsky

发明人： Gunther Lehmann ,  Gerd Frankowsky

IPC分类号： G11C700

CPC分类号： G11C29/812

摘要： Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

摘要翻译： 交付表示设备的阵列部分中的故障元素的地址信息。 各故障地址位值存储在多个保险丝中。 接收与另一地址的一部分的相应值相关联的信号。 当接收到信号时，其中一个故障地址位值从保险丝之一传送到相应的锁存电路。 锁存电路从至少两个保险丝接收故障地址位值。 其中一个故障地址位值是根据与信号相关的值来选择的。 锁存电路被激活以传送故障地址位值。

公开(公告)号：US08143694B2

公开(公告)日：2012-03-27

申请号：US12131134

申请日：2008-06-02

申请人： Vianney Choserot ,  Gunther Lehmann ,  Franz Ungar

发明人： Vianney Choserot ,  Gunther Lehmann ,  Franz Ungar

IPC分类号： H01L23/52

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.

摘要翻译： 本文提供了与保险丝装置，包括熔丝装置的集成电路，实现熔丝装置的方法和编程熔丝装置的方法相关的实施方式。

公开(公告)号：US07633787B2

公开(公告)日：2009-12-15

申请号：US11661582

申请日：2005-08-18

申请人： Siddarth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

发明人： Siddarth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

IPC分类号： G11C17/00

CPC分类号： G11C17/12 ,  G11C2207/2227

摘要： The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.

摘要翻译： 本发明涉及一种ROM存储单元，包括连接到字线的第一端子，包括第二端子并包括第三端子，第二端子连接到位线和/或第三端子连接到电源线 预充电第三个终端。 根据本发明的ROM存储器单元的特征在于，在待机操作模式中，相同的参考电位在每种情况下都应用于第一端子，第二端子和/或第三端子。 本发明还涉及一种包括这种ROM存储器单元的ROM存储器组件，以及一种用于从ROM存储单元读取的方法。