公开(公告)号：US20050024090A1

公开(公告)日：2005-02-03

申请号：US10631394

申请日：2003-07-31

申请人： Hartmud Terletzki ,  Gerd Frankowsky ,  Gunther Lehmann

发明人： Hartmud Terletzki ,  Gerd Frankowsky ,  Gunther Lehmann

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K17/163 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018585

摘要： A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

摘要翻译： 提供了一种系统和方法，用于控制芯片外驱动电路的阻抗和电流，以匹配由驱动器驱动的负载，并减少芯片外驱动电路中的噪声和振铃。 驱动器包括用于将驱动器的输出切换到高电压的上拉晶体管，用于将驱动器的输出切换到低电压的下拉晶体管，耦合到上拉晶体管的第一电流镜晶体管，用于控制 当驱动器的输出处于高电压时，电流传输到连接到驱动器的负载;以及耦合到下拉晶体管的第二电流镜晶体管，用于当驱动器的输出处于该状态时控制传输到负载的电流 低电压。 此外，驱动器可以包括为具有受控转换速率的上拉晶体管提供栅极信号的第一预驱动器，以及为具有受控转换速率的下拉晶体管提供栅极信号的第二预驱动器。

公开(公告)号：US06608783B2

公开(公告)日：2003-08-19

申请号：US10034625

申请日：2001-12-27

申请人： Gerd Frankowsky ,  Gunther Lehmann ,  Hartmud Terletzki

发明人： Gerd Frankowsky ,  Gunther Lehmann ,  Hartmud Terletzki

IPC分类号： G11C700

CPC分类号： G11C11/4096 ,  G11C7/1006 ,  G11C7/18 ,  G11C11/4097

摘要： A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

摘要翻译： 提供具有存储器单元的行和列阵列的存储器。 存储器包括多个读出放大器，每个读出放大器具有真正的终端和补码终端。 存储器还包括多对扭绞位线，每对线对中的每一对被耦合到多个读出放大器中对应的一个读出放大器的真实和补充端子。 提供多个字线，每个字线连接到存储器单元的行中相应的一行。 地址逻辑部分由馈送到位线的列地址信号和馈送到字线的行地址信号馈送，用于根据馈送的行和列地址信号产生反相/非反相信号。 存储器包括多个反相器，每个反相器被耦合到读出放大器中的对应的一个，用于根据由地址逻辑产生的反相/非反相信号选择性地反转馈送到读出放大器或从读出放大器读取的数据。

公开(公告)号：US06730989B1

公开(公告)日：2004-05-04

申请号：US09596130

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06815803B1

公开(公告)日：2004-11-09

申请号：US09596129

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06853233B1

公开(公告)日：2005-02-08

申请号：US09659872

申请日：2000-09-13

申请人： Hartmud Terletzki ,  Gerd Frankowsky

发明人： Hartmud Terletzki ,  Gerd Frankowsky

IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/09429

摘要： A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1 V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

摘要翻译： 电平移位电路包括响应于在第一电压电平（例如，接地）和第二电压电平（例如，2.1V）之间变化的输入逻辑信号的电平移位部分。 电平移位部分在输出端提供输出逻辑信号。 输出逻辑信号在第一电压电平和第三电压电平（例如，2.5V）之间变化。 电路还包括使能/禁用部分，其中第一部分耦合在电平移位部分和第一参考电压节点（例如接地）之间，第二部分耦合在电平移位部分和第三参考电压节点之间。 启用/禁用部分响应于来自使能/禁止信号的禁用模式指示，使得输出端子被放置在与输入逻辑信号的逻辑状态无关的较高输出阻抗条件下。

公开(公告)号：US06400650B1

公开(公告)日：2002-06-04

申请号：US09687883

申请日：2000-10-13

申请人： Gerd Frankowsky ,  Hartmud Terletzki

发明人： Gerd Frankowsky ,  Hartmud Terletzki

IPC分类号： G04F800

CPC分类号： G01R31/31724 ,  G01R29/0273 ,  G01R31/3016 ,  G01R31/3187 ,  G01R31/31937

摘要： A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

摘要翻译： 提供了包括产生脉冲的电路的半导体电路。 提供多个n个延迟元件，每个延迟元件通过脉冲并联启用和禁用。 每个延迟元件适于将脉冲从输入传输到输出，脉冲在不同时间到达相应的输出。 提供了多个n-1个检测器，每个检测器具有耦合到相应的延迟元件的输入的输入。 响应于接收脉冲的一部分，每个检测器适于将其输出的状态从多个状态设置到预定状态。 检测器的输出耦合到半导体电路的输出引脚。 提供了一种测试器，其适于耦合到半导体输出引脚并检测检测器输出的状态。

公开(公告)号：US07173473B2

公开(公告)日：2007-02-06

申请号：US11041464

申请日：2005-01-24

申请人： Hartmud Terletzki ,  Gerd Frankowsky

发明人： Hartmud Terletzki ,  Gerd Frankowsky

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/09429

摘要： A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

摘要翻译： 电平移位电路包括电平移位部分，其响应于在第一电压电平（例如，接地）和第二电压电平（例如，2.1V）之间变化的输入逻辑信号。 电平移位部分在输出端提供输出逻辑信号。 输出逻辑信号在第一电压电平和第三电压电平（例如，2.5V）之间变化。 电路还包括使能/禁用部分，其中第一部分耦合在电平移位部分和第一参考电压节点（例如接地）之间，第二部分耦合在电平移位部分和第三参考电压节点之间。 启用/禁用部分响应于来自使能/禁止信号的禁用模式指示，使得输出端子被放置在与输入逻辑信号的逻辑状态无关的较高输出阻抗条件下。

公开(公告)号：US07060529B2

公开(公告)日：2006-06-13

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/50 ,  H01L21/30

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US20050001298A1

公开(公告)日：2005-01-06

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/8242 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L27/105 ,  H01L23/544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06324125B1

公开(公告)日：2001-11-27

申请号：US09281020

申请日：1999-03-30

申请人： Gerd Frankowsky ,  Hartmud Terletzki

发明人： Gerd Frankowsky ,  Hartmud Terletzki

IPC分类号： G04F1000

CPC分类号： G01R31/31724 ,  G01R29/0273 ,  G01R31/3016 ,  G01R31/3187 ,  G01R31/31937

摘要： A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

摘要翻译： 提供了包括产生脉冲的电路的半导体电路。 提供多个n个延迟元件，每个延迟元件通过脉冲并联启用和禁用。 每个延迟元件适于将脉冲从输入传输到输出，脉冲在不同时间到达相应的输出。 提供了多个n-1个检测器，每个检测器具有耦合到相应的延迟元件的输入的输入。 响应于接收脉冲的一部分，每个检测器适于将其输出的状态从多个状态设置到预定状态。 检测器的输出耦合到半导体电路的输出引脚。 提供了一种测试器，其适于耦合到半导体输出引脚并检测检测器输出的状态。