公开(公告)号：US06740587B2

公开(公告)日：2004-05-25

申请号：US09949853

申请日：2001-09-12

申请人： Won-Sang Song ,  Jeong-Hwan Yang ,  In-Sun Park ,  Byoung-Moon Yoon

发明人： Won-Sang Song ,  Jeong-Hwan Yang ,  In-Sun Park ,  Byoung-Moon Yoon

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

摘要翻译： 本发明提供一种具有金属硅化物层的半导体器件和用于形成金属硅化物层的方法，该半导体器件具有金属硅化物半导体接触结构，其中半导体器件包括衬底，具有开口的绝缘层， 使用具有第一相和第二相的天然金属硅化物形成金属硅化物层，在其上形成导电层。 第二相具有与第一相的第二化学计量组成比不同的第一化学计量组成比。 第一相的金属硅化物层与硅之间的反应导致第二相的金属硅化物层具有高相稳定性和低电阻。

公开(公告)号：US20060232191A1

公开(公告)日：2006-10-19

申请号：US11377463

申请日：2006-03-16

申请人： Jeong-Hwan Yang

发明人： Jeong-Hwan Yang

IPC分类号： H01J1/62

CPC分类号： H01J29/02 ,  H01J29/467 ,  H01J29/48 ,  H01J31/127

摘要： An active matrix display comprising an array of gate-controlled surface-conduction electron-emitter devices (GC_SEDs). Each gate-controlled_surface-conduction electron-emitter device (GC_SED) comprises a first electrode, and a pair of (second and third) electrodes that are insulated from the first electrode and that are spaced apart from each other to bound an electron-emitting area overlapping the first electrode. The potential barrier in the electron-emitting area (slit) between the second and third electrodes is modulated (controlled, switched) by applying a voltage to the first electrode that serves as a gate that effectively controls the tunneling of the electrons, between the second and third electrodes. Efficient electron tunneling is allowed through modulation of potential barrier by the first electrode functioning as a gate even though the distance (width of the electron-emitting area, slit) between the second and third electrodes may be significantly more than 10 nanometers.

摘要翻译： 一种有源矩阵显示器，包括栅极控制的表面传导电子发射器件（GC_SED）阵列。 每个栅极控制的表面传导电子发射器件（GC_SED）包括第一电极和一对（第二和第三）电极，其与第一电极绝缘并且彼此间隔开以结合电子发射区域 与第一电极重叠。 在第二和第三电极之间的电子发射区（狭缝）中的势垒通过向用作有效控制电子的隧穿的第一电极施加电压而被调制（控制，切换），第二 和第三电极。 即使第二电极和第三电极之间的距离（电子发射区域，狭缝的宽度）可能明显大于10纳米，通过用作栅极的第一电极的势垒的调制允许有效的电子隧穿。

公开(公告)号：US07129517B2

公开(公告)日：2006-10-31

申请号：US10801651

申请日：2004-03-17

申请人： Jeong-Hwan Yang

发明人： Jeong-Hwan Yang

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/785 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

摘要： To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

摘要翻译： 为了减少通过沟道的电流损耗并提高电子迁移率，第一半导体层和第二半导体层（依次形成在半导体衬底上）具有不同的晶格特性。 可以蚀刻第一半导体层和第二半导体层以形成第一半导体图案。 可以在第一半导体图案之上形成具有与第一半导体层基本相同的晶格特性的第三半导体层。 然后可以蚀刻第三半导体层以形成第二半导体图案。 可以在第二半导体图案上形成栅极。 因此，可以增加第二半导体图案和栅极图案之间的接触表面以减小电流损耗。 此外，可以改变晶格特性以改善半导体层的电子迁移率。

公开(公告)号：US07932154B2

公开(公告)日：2011-04-26

申请号：US12007097

申请日：2008-01-07

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L21/334

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。

公开(公告)号：US07227175B2

公开(公告)日：2007-06-05

申请号：US11494445

申请日：2006-07-28

申请人： Jeong-Hwan Yang

发明人： Jeong-Hwan Yang

IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

摘要： To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

摘要翻译： 为了减小通过沟道的电流损耗并提高电子迁移率，第一半导体层和第二半导体层（依次形成在半导体衬底上）具有不同的晶格特性。 可以蚀刻第一半导体层和第二半导体层以形成第一半导体图案。 可以在第一半导体图案之上形成具有与第一半导体层基本相同的晶格特性的第三半导体层。 然后可以蚀刻第三半导体层以形成第二半导体图案。 可以在第二半导体图案上形成栅极。 因此，可以增加第二半导体图案和栅极图案之间的接触表面以减小电流损耗。 此外，可以改变晶格特性以改善半导体层的电子迁移率。

公开(公告)号：US07151019B2

公开(公告)日：2006-12-19

申请号：US11494470

申请日：2006-07-28

申请人： Jeong-Hwan Yang

发明人： Jeong-Hwan Yang

IPC分类号： H01L21/338 ,  H01L21/00 ,  H01L21/76 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

摘要： To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

摘要翻译： 为了减小通过沟道的电流损耗并提高电子迁移率，第一半导体层和第二半导体层（依次形成在半导体衬底上）具有不同的晶格特性。 可以蚀刻第一半导体层和第二半导体层以形成第一半导体图案。 可以在第一半导体图案之上形成具有与第一半导体层基本相同的晶格特性的第三半导体层。 然后可以蚀刻第三半导体层以形成第二半导体图案。 可以在第二半导体图案上形成栅极。 因此，可以增加第二半导体图案和栅极图案之间的接触表面以减小电流损耗。 此外，可以改变晶格特性以改善半导体层的电子迁移率。

公开(公告)号：US08159006B2

公开(公告)日：2012-04-17

申请号：US12008232

申请日：2008-01-09

申请人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US20080108197A1

公开(公告)日：2008-05-08

申请号：US12007097

申请日：2008-01-07

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L21/334

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。

公开(公告)号：US07320920B2

公开(公告)日：2008-01-22

申请号：US11097281

申请日：2005-04-04

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L21/334

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。

公开(公告)号：US20060011965A1

公开(公告)日：2006-01-19

申请号：US11097281

申请日：2005-04-04

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。