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    Nonvolatile memory device having wear-leveling control and method of operating the same
    1.
    发明授权
    Nonvolatile memory device having wear-leveling control and method of operating the same 有权
    具有磨损均衡控制的非易失性存储器件及其操作方法

    公开(公告)号：US09372790B2

    公开(公告)日：2016-06-21

    申请号：US13954135

    申请日：2013-07-30

    申请人： Wonseok Lee ,  Youngkug Moon ,  Taek-Sung Kim

    发明人： Wonseok Lee ,  Youngkug Moon ,  Taek-Sung Kim

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7211

    摘要： A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.

    摘要翻译： 提供了一种用于控制非易失性存储器件中的写入操作以提供损耗均衡的方法，其中非易失性存储器件包括多个存储器块。 所述方法包括：读取至少所述多个存储块的所选存储块的写入指示信息; 基于所选择的存储块的写入指示信息，确定要存储在所选存储器块中的数据的写入顺序是升序还是降序; 以及当所述数据的写入顺序被确定为升序时，以升序生成所选择的存储器块中的存储器区域的地址，并且当所述写入顺序为低时产生所选存储器块中的存储器区域的地址 被确定为降序。

    Variable resistance memory device and system
    7.
    发明授权
    Variable resistance memory device and system 有权
    可变电阻存储器件和系统

    公开(公告)号：US07952956B2

    公开(公告)日：2011-05-31

    申请号：US12417679

    申请日：2009-04-03

    申请人： Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

    发明人： Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

    IPC分类号： G11C8/00

    CPC分类号： G11C16/08 ,  G11C8/12

    摘要： A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

    摘要翻译： 半导体存储器件包括具有分成第一和第二区域的多个可变电阻存储单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。