公开(公告)号：US20240333307A1

公开(公告)日：2024-10-03

申请号：US18128943

申请日：2023-03-30

Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1174 ,  H03M13/616

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

公开(公告)号：US20250117298A1

公开(公告)日：2025-04-10

申请号：US18376724

申请日：2023-10-04

Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

Inventor： Kumar RAHUL ,  Santosh YACHARENI ,  Pierre MAILLARD ,  Mrinmoy GOSWAMI ,  Tabrez ALAM ,  Gokul Puthenpurayil RAVINDRAN ,  Md HUSSAIN ,  Sanat Kumar DUBEY ,  John J. WUU

IPC: G06F11/16 ,  G06F11/07

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

公开(公告)号：US20240201863A1

公开(公告)日：2024-06-20

申请号：US18082223

申请日：2022-12-15

Applicant: XILINX, INC.

Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI ,  Nui CHONG ,  Cheang Whang CHANG

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.