公开(公告)号：US20240333307A1

公开(公告)日：2024-10-03

申请号：US18128943

申请日：2023-03-30

申请人： XILINX, INC. ,  Advanced Micro Devices, Inc.

发明人： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1174 ,  H03M13/616

摘要： An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

公开(公告)号：US20240221808A1

公开(公告)日：2024-07-04

申请号：US18090574

申请日：2022-12-29

申请人： XILINX, INC.

发明人： Kumar RAHUL ,  Santosh YACHARENI ,  Mahendrakumar GUNASEKARAN ,  Mohammad ANEES

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1069 ,  G11C7/109

摘要： An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

公开(公告)号：US20240201863A1

公开(公告)日：2024-06-20

申请号：US18082223

申请日：2022-12-15

申请人： XILINX, INC.

发明人： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI ,  Nui CHONG ,  Cheang Whang CHANG

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

摘要： A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.