公开(公告)号：US20240321793A1

公开(公告)日：2024-09-26

申请号：US18125660

申请日：2023-03-23

申请人： XILINX, INC.

发明人： Yun WU ,  Henley LIU ,  Myongseob KIM ,  Chris LEE ,  Cheang Whang CHANG

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/06132 ,  H01L2224/06177 ,  H01L2224/06179 ,  H01L2224/16227 ,  H01L2924/381 ,  H01L2924/3841

摘要： An integrated circuit (IC) die includes a body having a dielectric layer and a plurality of contact pads formed on the dielectric layer. The IC die also includes a passivation layer disposed on the dielectric layer. The passivation layer has a plurality of openings exposing the plurality of contact pads. A plurality of inner under-bump-metallurgy (“UBM”) structures are disposed on a first portion of the plurality of openings, and a plurality of outer UBM structures are disposed on a second portion of the plurality of openings. The plurality of inner UBM structures have uniform spacing in a direction parallel to an edge of the body. The plurality of outer UBM structures are positioned around the plurality of inner UBM structures, and each of the plurality of outer UBM structures having a longitudinal axis directed toward a central area of the IC die.

公开(公告)号：US20210265312A1

公开(公告)日：2021-08-26

申请号：US16798267

申请日：2020-02-21

申请人： XILINX, INC.

发明人： Myongseob KIM ,  Henley LIU ,  Cheang Whang CHANG

IPC分类号： H01L25/065 ,  H01L21/50 ,  H01L25/00

摘要： An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

公开(公告)号：US20230140675A1

公开(公告)日：2023-05-04

申请号：US17515354

申请日：2021-10-29

申请人： XILINX, INC.

发明人： Myongseob KIM ,  Henley LIU ,  Cheang Whang CHANG

IPC分类号： H01L25/065 ,  H01L21/66 ,  H01L23/00

摘要： An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

公开(公告)号：US20240201863A1

公开(公告)日：2024-06-20

申请号：US18082223

申请日：2022-12-15

申请人： XILINX, INC.

发明人： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI ,  Nui CHONG ,  Cheang Whang CHANG

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

摘要： A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.