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    ECC OPTIMIZATION
    1.
    发明公开
    ECC OPTIMIZATION 审中-公开

    公开(公告)号：US20240333307A1

    公开(公告)日：2024-10-03

    申请号：US18128943

    申请日：2023-03-30

    Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

    Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1174 ,  H03M13/616

    Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

    SINGLE EVENT UPSET TOLERANT MEMORY DEVICE
    3.
    发明公开
    SINGLE EVENT UPSET TOLERANT MEMORY DEVICE 审中-公开

    公开(公告)号：US20240201863A1

    公开(公告)日：2024-06-20

    申请号：US18082223

    申请日：2022-12-15

    Applicant: XILINX, INC.

    Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI ,  Nui CHONG ,  Cheang Whang CHANG

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

    Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

    ADAPTIVE WRITE SCHEME FOR MEMORY DEVICES
    4.
    发明申请
    ADAPTIVE WRITE SCHEME FOR MEMORY DEVICES 有权

    公开(公告)号：US20250061926A1

    公开(公告)日：2025-02-20

    申请号：US18235739

    申请日：2023-08-18

    Applicant: XILINX, INC.

    Inventor： Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Narendra Kumar PULIPATI

    IPC: G11C7/08 ,  G11C7/10 ,  G11C7/20

    Abstract: Memory driver circuitry for driving a memory cell or cells of a memory device includes first driver path circuitry and selection circuitry. The first driver path circuitry includes driver circuitry that outputs a first signal and selection circuitry that receives the first signal and a second signal, and outputs a first selected signal. The first selected signal is a selected one of the first signal and the second signal. The selection circuitry of the memory driver circuitry receives a third signal and a fourth signal, and outputs a bias voltage signal to header circuitry of a memory cell. The bias voltage signal is a selected one of the third signal and the fourth signal. The third signal corresponds to the first selected signal.

    THIN OXIDE LOW VOLTAGE TO HIGH VOLTAGE LEVEL SHIFTERS
    5.
    发明申请
    THIN OXIDE LOW VOLTAGE TO HIGH VOLTAGE LEVEL SHIFTERS 有权

    公开(公告)号：US20250047285A1

    公开(公告)日：2025-02-06

    申请号：US18229152

    申请日：2023-08-01

    Applicant: XILINX, INC.

    Inventor： Lakshmi Venkata Satya Lalitha Indumathi JANASWAMY ,  Narendra Kumar PULIPATI ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA

    IPC: H03K19/0185 ,  H03K3/037

    Abstract: A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.

    SINGLE PORT MEMORY WITH MUTLITPLE MEMORY OPERATIONS PER CLOCK CYCLE
    8.
    发明公开
    SINGLE PORT MEMORY WITH MUTLITPLE MEMORY OPERATIONS PER CLOCK CYCLE 审中-公开

    公开(公告)号：US20240221808A1

    公开(公告)日：2024-07-04

    申请号：US18090574

    申请日：2022-12-29

    Applicant: XILINX, INC.

    Inventor： Kumar RAHUL ,  Santosh YACHARENI ,  Mahendrakumar GUNASEKARAN ,  Mohammad ANEES

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/109

    Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

    REFERENCE LESS GLITCH DETECTION CIRCUITRY WITH AUTOCALIBRATION
    9.
    发明申请
    REFERENCE LESS GLITCH DETECTION CIRCUITRY WITH AUTOCALIBRATION 有权

    公开(公告)号：US20230049371A1

    公开(公告)日：2023-02-16

    申请号：US17401875

    申请日：2021-08-13

    Applicant: XILINX, INC.

    Inventor： Sourabh SHARMA ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Santosh YACHARENI

    IPC: G01R31/30 ,  G01R11/24 ,  G06F21/76 ,  G01R22/06

    Abstract: Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.

    MULTI-CHIP STACKED DEVICES
    10.
    发明申请
    MULTI-CHIP STACKED DEVICES 有权

    公开(公告)号：US20210217729A1

    公开(公告)日：2021-07-15

    申请号：US16741319

    申请日：2020-01-13

    Applicant: XILINX, INC.

    Inventor： Anil Kumar KANDALA ,  Vijay Kumar KOGANTI ,  Santosh YACHARENI

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L23/528

    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

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