公开(公告)号：US08359074B1

公开(公告)日：2013-01-22

申请号：US11546605

申请日：2006-10-11

申请人： Xiaodong Jin ,  King Chun Tsai ,  Yonghua Song

发明人： Xiaodong Jin ,  King Chun Tsai ,  Yonghua Song

IPC分类号： H04B1/38

CPC分类号： H04B1/1615 ,  H03F1/26 ,  H03F1/30 ,  H03F1/305 ,  H03F3/24 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/453 ,  H04W52/0274 ,  Y02D70/142 ,  Y02D70/40

摘要： A dummy circuit is provided to which a bias circuit of an low noise amplifier (LNA) can be coupled to during power down of the LNA. The dummy circuit maintains the bias circuit at an approximately normal operating state to reduce wake up time of the LNA.

摘要翻译： 提供虚拟电路，在LNA的断电期间，可以将低噪声放大器（LNA）的偏置电路耦合到该伪电路。 虚拟电路将偏置电路保持在大致正常的操作状态，以减少LNA的唤醒时间。

公开(公告)号：US07184799B1

公开(公告)日：2007-02-27

申请号：US10753101

申请日：2004-01-06

申请人： Xiaodong Jin ,  King Chun Tsai ,  Yonghua Song

发明人： Xiaodong Jin ,  King Chun Tsai ,  Yonghua Song

IPC分类号： H04B1/38 ,  H04B1/16

CPC分类号： H04B1/1615 ,  H03F1/26 ,  H03F1/30 ,  H03F1/305 ,  H03F3/24 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/453 ,  H04W52/0274 ,  Y02D70/142 ,  Y02D70/40

摘要： A dummy circuit is provided to which a bias circuit of a low noise amplifier (LNA) can be coupled to during power down of the LNA. The dummy circuit maintains the bias circuit at an approximately normal operating state to reduce wake up time of the LNA.

摘要翻译： 提供虚拟电路，在LNA的断电期间，低噪声放大器（LNA）的偏置电路可耦合到该虚拟电路。 虚拟电路将偏置电路保持在大致正常的操作状态，以减少LNA的唤醒时间。

公开(公告)号：US07463095B1

公开(公告)日：2008-12-09

申请号：US11890738

申请日：2007-08-07

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

IPC分类号： H03F3/04

CPC分类号： H03G1/0029 ,  H03G1/007 ,  H03G2201/103

摘要： An analog signal processing circuit comprises a bias circuit, a first circuit including a control input that communicates with the bias circuit, a first terminal that generates an output current, and a second terminal, and a device that communicates with the second terminal of the first circuit, that includes a variable resistor, and that has a resistance that is modulated in response to an input signal to the analog signal processing circuit.

摘要翻译： 模拟信号处理电路包括偏置电路，包括与偏置电路通信的控制输入的第一电路，产生输出电流的第一端子和第二端子，以及与第一端子的第二端子通信的装置 电路，其包括可变电阻器，并且具有响应于模拟信号处理电路的输入信号而被调制的电阻。

公开(公告)号：US06977444B1

公开(公告)日：2005-12-20

申请号：US11034093

申请日：2005-01-12

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

IPC分类号： H01L23/48 ,  H01L23/49 ,  H01L23/60 ,  H01L23/66

CPC分类号： H01L24/49 ,  H01L23/60 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/484 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： An input circuit for an integrated circuit (IC), which is mounted on a package having an input pin, rejects signal energy at a first frequency. A first bondwire arranged on the package has one end that communicates with the pin and an opposite end that communicates with components of the IC. A second bondwire located on the package has one end that communicates with the pin and an opposite end that communicates with a capacitance. The capacitance and an inductance of the first and second bondwires resonate at the first frequency to reject signal energy at the first frequency. Bondwires are also used to eliminate external components such as resonant components and impedance matching circuits to reduce cost.

摘要翻译： 用于集成电路（IC）的输入电路，其安装在具有输入引脚的封装上，以第一频率拒绝信号能量。 布置在封装上的第一接合线具有与引脚连通的一端和与IC的部件连通的相对端。 位于封装上的第二接合线具有与销连通的一端和与电容连通的相对端。 第一和第二键合线的电容和电感以第一频率谐振以在第一频率处抑制信号能量。 Bondwires也用于消除诸如谐振元件和阻抗匹配电路的外部元件，以降低成本。

公开(公告)号：US07751164B1

公开(公告)日：2010-07-06

申请号：US12154706

申请日：2008-05-27

申请人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse ,  King Chun Tsai

发明人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse ,  King Chun Tsai

IPC分类号： H02H9/00 ,  H02H3/22 ,  H03K17/16

CPC分类号： H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0251 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/484 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for reducing a parasitic capacitance of an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) includes providing an ESD protection circuit including a plurality of transistors; coupling one end of a resistor to a shared drain of the plurality of transistors; and coupling an opposite end of the resistor to at least one of an input pad of the IC, a blocking capacitor of the IC and a transistor in the IC.

摘要翻译： 一种用于降低集成电路（IC）的静电放电（ESD）保护电路的寄生电容的方法包括提供包括多个晶体管的ESD保护电路; 将电阻器的一端耦合到所述多个晶体管的共享漏极; 以及将所述电阻器的相对端耦合到所述IC的输入焊盘，所述IC的隔离电容器和所述IC中的晶体管中的至少一个。

公开(公告)号：US07230491B1

公开(公告)日：2007-06-12

申请号：US11175943

申请日：2005-07-05

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

IPC分类号： H03G3/10

CPC分类号： H03G1/0029 ,  H03G1/007 ,  H03G2201/103

摘要： A bias circuit for biasing a linear input stage of an amplifier comprises a first MOS device having a size. A second MOS device has a size and is arranged with the first MOS device in a cascode configuration. The second MOS device is operated in a saturation region. A third MOS device has a size and biases the first MOS device in a triode region. A bias switch ratio of the size of the first MOS device to the size of the third MOS device is greater than one.

摘要翻译： 用于偏置放大器的线性输入级的偏置电路包括具有大小的第一MOS器件。 第二MOS器件具有尺寸并与第一MOS器件配置成共源共栅配置。 第二MOS器件在饱和区域中工作。 第三MOS器件具有尺寸并偏置三极管区域中的第一MOS器件。 第一MOS器件的尺寸与第三MOS器件的尺寸的偏置开关比大于1。

公开(公告)号：US06987326B1

公开(公告)日：2006-01-17

申请号：US11033202

申请日：2005-01-11

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

IPC分类号： H01L23/49

CPC分类号： H01L24/49 ,  H01L23/60 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/484 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： An impedance matching circuit is provided for an IC arranged on a package that matches an impedance of an external load. The circuit includes a package, an IC that is arranged on the package, and an impedance matching circuit. The impedance matching circuit includes a first bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with said IC, a capacitance element arranged on the IC, and a second bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with one end of said capacitance element.

摘要翻译： 针对布置在与外部负载的阻抗匹配的封装上的IC提供阻抗匹配电路。 电路包括封装，布置在封装上的IC和阻抗匹配电路。 阻抗匹配电路包括布置在封装上的第一接合线，其具有与外部负载连通的一端和与所述IC连通的相对端，布置在IC上的电容元件和布置在封装上的第二接合线， 与外部负载连通的一端和与所述电容元件的一端连通的相对端。

公开(公告)号：US06911739B1

公开(公告)日：2005-06-28

申请号：US10397402

申请日：2003-03-26

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien ,  Shuran Wei

IPC分类号： H01L23/48 ,  H01L23/49 ,  H01L23/60 ,  H01L23/66

CPC分类号： H01L24/49 ,  H01L23/60 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/484 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： An input circuit for an integrated circuit (IC), which is mounted on a package having an input pin, rejects signal energy at a first frequency. A first bondwire arranged on the package has one end that communicates with the pin and an opposite end that communicates with components of the IC. A second bondwire located on the package has one end that communicates with the pin and an opposite end that communicates with a capacitance. The capacitance and an inductance of the first and second bondwires resonate at the first frequency to reject signal energy at the first frequency. Bondwires are also used to eliminate external components such as resonant components and impedance matching circuits to reduce cost.

公开(公告)号：US08031006B1

公开(公告)日：2011-10-04

申请号：US12567855

申请日：2009-09-28

申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

IPC分类号： H03F3/04

CPC分类号： H03G1/0029 ,  H03G1/007 ,  H03G2201/103

摘要： A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.

摘要翻译： 低噪声放大器包括输入级。 输入级包括被配置为接收输入信号的第一设备。 第二设备连接到第一设备。 第二装置具有预定的输入阻抗。 输入级被配置为使得到第一器件的输入信号的变化导致第一器件的电导的线性比例变化。 由于第二装置的预定输入阻抗，第一装置和第二装置之间的连接处的电压保持基本恒定。

公开(公告)号：US08000067B1

公开(公告)日：2011-08-16

申请号：US10811031

申请日：2004-03-26

申请人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse ,  King Chun Tsai

发明人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse ,  King Chun Tsai

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) circuit operable to protect an internal circuit from ESD events and protect the internal circuit from high-side supply noise.

摘要翻译： 静电放电（ESD）电路可操作以保护内部电路免受ESD事件的影响，并保护内部电路免受高端电源噪声的影响。