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    Mechanisms and methods for using data access patterns
    2.
    发明申请
    Mechanisms and methods for using data access patterns 有权
    使用数据访问模式的机制和方法

    公开(公告)号：US20070088919A1

    公开(公告)日：2007-04-19

    申请号：US11250288

    申请日：2005-10-14

    申请人： Xiaowei Shen ,  Hazim Shafi

    发明人： Xiaowei Shen ,  Hazim Shafi

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862 ,  G06F12/0815 ,  G06F2212/6026

    摘要： The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a memory region and passes the data access pattern information to hardware via proper data access pattern instructions defined in the data access pattern interface. Hardware maintains the data access pattern information properly when the data access pattern instructions are executed. Hardware can then use the data access pattern information to dynamically detect data access patterns for a memory region throughout the program execution, and voluntarily invoke appropriate memory and cache operations such as pre-fetch, pre-send, acquire-ownership and release-ownership. Further, hardware can provide runtime monitoring information for memory accesses to the memory region, wherein the runtime monitoring information indicates whether the software-provided data access pattern information is accurate.

    摘要翻译： 本发明包括数据访问模式接口，其允许软件指定一个或多个数据访问模式，例如流访问模式，指针追踪模式和生产者 - 消费者模式。 软件检测存储器区域的数据访问模式，并通过数据访问模式界面中定义的适当的数据访问模式指令将数据访问模式信息传递给硬件。 当执行数据访问模式指令时，硬件正确地维护数据访问模式信息。 然后，硬件可以使用数据访问模式信息在整个程序执行期间动态地检测存储器区域的数据访问模式，并且主动地调用适当的存储器和缓存操作，例如预取，预发送，获取所有权和释放所有权。 此外，硬件可以提供用于存储器访问存储器区域的运行时监视信息，其中运行时监视信息指示软件提供的数据访问模式信息是否准确。

    Methods and arrangements to manage on-chip memory to reduce memory latency
    3.
    发明申请
    Methods and arrangements to manage on-chip memory to reduce memory latency 有权
    管理片上存储器以减少内存延迟的方法和安排

    公开(公告)号：US20060155886A1

    公开(公告)日：2006-07-13

    申请号：US11032876

    申请日：2005-01-11

    申请人： Dilma da Silva ,  Elmootazbellah Elnozahy ,  Orran Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Tremaine

    发明人： Dilma da Silva ,  Elmootazbellah Elnozahy ,  Orran Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Tremaine

    IPC分类号： G06F3/00

    CPC分类号： G06F12/08 ,  G06F12/0893 ,  G06F2212/251 ,  G06F2212/253

    摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

    摘要翻译： 考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。 许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。 因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。 几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

    Mechanisms and methods for using data access patterns
    6.
    发明授权
    Mechanisms and methods for using data access patterns 有权
    使用数据访问模式的机制和方法

    公开(公告)号：US07395407B2

    公开(公告)日：2008-07-01

    申请号：US11250288

    申请日：2005-10-14

    申请人： Xiaowei Shen ,  Hazim Shafi

    发明人： Xiaowei Shen ,  Hazim Shafi

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0815 ,  G06F2212/6026

    摘要： The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a memory region and passes the data access pattern information to hardware via proper data access pattern instructions defined in the data access pattern interface. Hardware maintains the data access pattern information properly when the data access pattern instructions are executed. Hardware can then use the data access pattern information to dynamically detect data access patterns for a memory region throughout the program execution, and voluntarily invoke appropriate memory and cache operations such as pre-fetch, pre-send, acquire-ownership and release-ownership. Further, hardware can provide runtime monitoring information for memory accesses to the memory region, wherein the runtime monitoring information indicates whether the software-provided data access pattern information is accurate.

    摘要翻译： 本发明包括数据访问模式接口，其允许软件指定一个或多个数据访问模式，例如流访问模式，指针追踪模式和生产者 - 消费者模式。 软件检测存储器区域的数据访问模式，并通过数据访问模式界面中定义的适当的数据访问模式指令将数据访问模式信息传递给硬件。 当执行数据访问模式指令时，硬件正确地维护数据访问模式信息。 然后，硬件可以使用数据访问模式信息在整个程序执行期间动态地检测存储器区域的数据访问模式，并且主动地调用适当的存储器和缓存操作，例如预取，预发送，获取所有权和释放所有权。 此外，硬件可以提供用于存储器访问存储器区域的运行时监视信息，其中运行时监视信息指示软件提供的数据访问模式信息是否准确。

    System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory
    7.
    发明授权
    System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory 有权
    用于重新配置具有与下级高速缓冲存储器的扇区相关联的访问位的高速缓冲存储器的系统和与上级高速缓冲存储器的扇区相关联的粒度位

    公开(公告)号：US08140764B2

    公开(公告)日：2012-03-20

    申请号：US12985726

    申请日：2011-01-06

    申请人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

    发明人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

    摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

    摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

    Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint
    8.
    发明授权
    Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint 有权
    基于分析运行时性能数据或软件提示的一个或多个特性的缓存重新配置

    公开(公告)号：US07913041B2

    公开(公告)日：2011-03-22

    申请号：US12130752

    申请日：2008-05-30

    申请人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

    发明人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

    摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

    摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

    COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES
    9.
    发明申请
    COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES 审中-公开
    计算机程序指导体系，系统和过程使用部分订购对存储器延迟的自适应响应

    公开(公告)号：US20090235035A1

    公开(公告)日：2009-09-17

    申请号：US12404957

    申请日：2009-03-16

    申请人： David F. Bacon ,  Xiaowei Shen

    发明人： David F. Bacon ,  Xiaowei Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F8/314 ,  G06F9/30076 ,  G06F9/30098

    摘要： The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.

    摘要翻译： 本发明广泛地考虑了编织物和纤维，高级编程结构，其有助于创建部分排序的程序，以解决不断增长的处理器速度和伴随的存储器延迟增加的持续趋势。 这些部分顺序可用于自适应地响应内存延迟。 显示了如何通过简单和便宜的指令集和微架构扩展来有效地支持这些构造。

    Adaptive mechanisms for supplying volatile data copies in multiprocessor systems
    10.
    发明授权
    Adaptive mechanisms for supplying volatile data copies in multiprocessor systems 失效
    用于在多处理器系统中提供易失性数据副本的自适应机制

    公开(公告)号：US07478197B2

    公开(公告)日：2009-01-13

    申请号：US11458192

    申请日：2006-07-18

    申请人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

    发明人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/507

    摘要： In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

    摘要翻译： 在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。 此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性变更为非易失性的易失性促进机制，或者根据某种降级策略将数据副本从非易失性变为不稳定。