公开(公告)号：US09075930B2

公开(公告)日：2015-07-07

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G06F13/42 ,  H03K19/177 ,  G11C16/26

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

公开(公告)号：US20140133246A1

公开(公告)日：2014-05-15

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

公开(公告)号：US08912829B1

公开(公告)日：2014-12-16

申请号：US13965021

申请日：2013-08-12

Applicant: Xilinx, Inc.

Inventor： James E. Ogden ,  James M. Simkins ,  Uma Durairajan ,  Subodh Kumar

IPC: H03L7/00 ,  H03L7/10 ,  H03K17/22 ,  H02M1/00

CPC classification number: G06F1/24 ,  H02M2001/0032 ,  H03K17/223

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract translation: 公开了一种用于使用同步复位脉冲来复位包括多个时钟域的电路的集成电路和方法。 例如，本公开的方法提供了一个同步到一个时钟的复位信号，采用同步信号并复位多个时钟域中的电路。 为了复位处于特定时钟域的电路的一部分，复位需要与特定域的时钟同步。