公开(公告)号：US20140089718A1

公开(公告)日：2014-03-27

申请号：US13625108

申请日：2012-09-24

Applicant: XILINX, INC.

Inventor： Julian M. Kain

IPC: G06F1/04

CPC classification number: H04L25/05 ,  G06F5/06 ,  H04L25/14

Abstract: An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency.

Abstract translation: 一种装置包括多个通道，其中每个通道包括异步缓冲器，等待时间确定块，抽头选择电路和可变延迟。 等待定位器被配置为识别来自信道之间的最长延迟，并且被耦合以向每个信道的抽头选择电路提供最长等待时间。 对于每个通道：等待时间确定块耦合到异步缓冲器以确定异步缓冲器的等待时间值; 抽头选择电路被耦合以接收延迟值和最长延迟; 分接选择电路耦合到可变延迟; 并且抽头选择电路被配置为响应于等待时间值和最长延迟来选择可变延迟的抽头的抽头。

公开(公告)号：US11922223B1

公开(公告)日：2024-03-05

申请号：US17170427

申请日：2021-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Lizhi Hou ,  Julian M. Kain

IPC: G06F9/50 ,  G06F9/38 ,  H04L9/06

CPC classification number: G06F9/5077 ,  G06F9/3836 ,  G06F9/3877 ,  H04L9/0643

Abstract: Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

公开(公告)号：US11561779B1

公开(公告)日：2023-01-24

申请号：US16996717

申请日：2020-08-18

Applicant: XILINX, INC.

Inventor： Julian M. Kain

IPC: G06F8/41 ,  G06F9/50

Abstract: An example method of implementing an application for a hardware accelerator having a programmable device coupled to memory is disclosed. The method includes compiling source code of the application to generate logical circuit descriptions of kernel circuits; determining resource availability in a dynamic region of programmable logic of the programmable device, the dynamic region exclusive of a static region of the programmable logic programmed with a host interface configured to interface a computing system having the hardware accelerator; determining resource utilization by the kernel circuits in the dynamic region; determining fitting solutions of the kernel circuits within the dynamic region, each of the fitting solutions defining connectivity of the kernel circuits to banks of the memory; adding a memory subsystem to the application based on a selected fitting solution of the fitting solutions; and generating a kernel image configured to program the dynamic region to implement the kernel circuits and the memory subsystem.

公开(公告)号：US11232247B1

公开(公告)日：2022-01-25

申请号：US17075364

申请日：2020-10-20

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain ,  Adam P. Donlin

IPC: G06F30/39 ,  G06F9/54 ,  G06F9/38 ,  G06F30/34

Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

公开(公告)号：US09497050B2

公开(公告)日：2016-11-15

申请号：US13625108

申请日：2012-09-24

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain

IPC: G06F1/04 ,  H04L25/05 ,  H04L25/14 ,  G06F5/06

CPC classification number: H04L25/05 ,  G06F5/06 ,  H04L25/14

Abstract: An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency.

Abstract translation: 一种装置包括多个通道，其中每个通道包括异步缓冲器，等待时间确定块，抽头选择电路和可变延迟。 等待定位器被配置为识别来自信道之间的最长延迟，并且被耦合以向每个信道的抽头选择电路提供最长等待时间。 对于每个通道：等待时间确定块耦合到异步缓冲器以确定异步缓冲器的等待时间值; 抽头选择电路被耦合以接收延迟值和最长延迟; 抽头选择电路耦合到可变延迟; 并且抽头选择电路被配置为响应于等待时间值和最长延迟来选择可变延迟的抽头的抽头。

公开(公告)号：US11474555B1

公开(公告)日：2022-10-18

申请号：US15684035

申请日：2017-08-23

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Julian M. Kain ,  Stephen P. Rozum ,  Khang K. Dao ,  Kyle Corbett

IPC: G06F1/10 ,  G06F13/10 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

公开(公告)号：US10817353B1

公开(公告)日：2020-10-27

申请号：US16225279

申请日：2018-12-19

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain ,  Adam P. Donlin

IPC: G06F30/34 ,  G06F9/54 ,  G06F9/38 ,  G06F30/39

Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

公开(公告)号：US10747516B1

公开(公告)日：2020-08-18

申请号：US16361037

申请日：2019-03-21

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain

IPC: G06F8/41 ,  G06F9/50

Abstract: An example method of implementing an application for a hardware accelerator having a programmable device coupled to memory is disclosed. The method includes compiling source code of the application to generate logical circuit descriptions of kernel circuits; determining resource availability in a dynamic region of programmable logic of the programmable device, the dynamic region exclusive of a static region of the programmable logic programmed with a host interface configured to interface a computing system having the hardware accelerator; determining resource utilization by the kernel circuits in the dynamic region; determining fitting solutions of the kernel circuits within the dynamic region, each of the fitting solutions defining connectivity of the kernel circuits to banks of the memory; adding a memory subsystem to the application based on a selected fitting solution of the fitting solutions; and generating a kernel image configured to program the dynamic region to implement the kernel circuits and the memory subsystem.