公开(公告)号：US12019964B1

公开(公告)日：2024-06-25

申请号：US17376892

申请日：2021-07-15

Applicant: Xilinx, Inc.

Inventor： Karthic P ,  Paul Kundarewich ,  Satish Sivaswamy ,  Meghraj Kalase ,  Vishal Tripathi ,  Srinivasan Dasasathyan ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang ,  Amish Pandya

IPC: G06F30/337 ,  G06F30/392 ,  G06N20/00

CPC classification number: G06F30/337 ,  G06F30/392 ,  G06N20/00

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

公开(公告)号：US20240111932A1

公开(公告)日：2024-04-04

申请号：US17959038

申请日：2022-10-03

Applicant: Xilinx, Inc.

Inventor： Satish Bachina ,  Karthic P ,  Vishal Tripathi ,  Srinivasan Dasasathyan

IPC: G06F30/32

CPC classification number: G06F30/32 ,  G06F2119/06

Abstract: Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the features. Each directive is associated with one of the sets of regressor models, and a combined score from each set of regressor models indicates a likelihood of satisfying a constraint. The directives are ranked based on the values indicated by the classifier models and scores from the sets of regressor models, and the circuit design is processed n the second phase of the implementation flow by the design tool using the directive having the highest rank.