公开(公告)号：US12019964B1

公开(公告)日：2024-06-25

申请号：US17376892

申请日：2021-07-15

Applicant: Xilinx, Inc.

Inventor： Karthic P ,  Paul Kundarewich ,  Satish Sivaswamy ,  Meghraj Kalase ,  Vishal Tripathi ,  Srinivasan Dasasathyan ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang ,  Amish Pandya

IPC: G06F30/337 ,  G06F30/392 ,  G06N20/00

CPC classification number: G06F30/337 ,  G06F30/392 ,  G06N20/00

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

公开(公告)号：US20240362393A1

公开(公告)日：2024-10-31

申请号：US18139659

申请日：2023-04-26

Applicant: Xilinx, Inc.

Inventor： Apurva Abhijit Mirashi ,  Veeresh Pratap Singh ,  Meghraj Kalase ,  Srinivasan Dasasathyan

IPC: G06F30/394 ,  G06F30/31 ,  G06F30/323 ,  G06F30/327 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/31 ,  G06F30/323 ,  G06F30/327 ,  G06F30/392

Abstract: A congestion prediction machine learning model is trained to generate, prior to placement, a prediction value indicative of a congestion level likely to result from placement and routing of a netlist based on features of the netlist. In response to the prediction value indicating the congestion level is greater than a threshold, a design tool determines an implementation-flow action and performs the implementation-flow action to generate implementation data that is suitable for making an integrated circuit.

公开(公告)号：US11714950B2

公开(公告)日：2023-08-01

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/327 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US20230034736A1

公开(公告)日：2023-02-02

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.