公开(公告)号：US10963170B2

公开(公告)日：2021-03-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US20200241770A1

公开(公告)日：2020-07-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US09018980B1

公开(公告)日：2015-04-28

申请号：US14303041

申请日：2014-06-12

Applicant: Xilinx, Inc.

Inventor： Uma Durairajan ,  Subodh Kumar ,  Michelle Zeng ,  Hsiao H. Chen

IPC: H03K19/00 ,  H03K3/012 ,  H03K19/0175 ,  G06F1/32 ,  G11C7/22

CPC classification number: H03K19/0016 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3275 ,  G11C7/222 ,  H03K3/012 ,  H03K19/017581 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

Abstract translation: 公开了一种与时钟发生器有关的装置。 时钟发生器被耦合以接收输入时钟信号，并进一步耦合以提供输出时钟信号。 地址和控制寄存器被耦合以接收地址信号和输出时钟信号。 接入发生器被耦合以接收输出时钟信号。 时钟发生器包括：耦合以接收输入时钟信号的输入节点; 至少一个脉冲发生器耦合到所述输入节点以接收所述输入时钟信号，并进一步耦合以提供时钟控制信号; 以及控制栅极，其耦合到所述输入节点以接收所述输入信号，并且还耦合到所述至少一个脉冲发生器以接收所述时钟控制信号。 时钟控制信号以高频模式的非切换状态和低频模式的切换状态被提供。