公开(公告)号：US20200066713A1

公开(公告)日：2020-02-27

申请号：US16110894

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/73 ,  H01L29/78 ,  H01L49/02

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

公开(公告)号：US09462674B1

公开(公告)日：2016-10-04

申请号：US14010059

申请日：2013-08-26

Applicant: Xilinx, Inc.

Inventor： Mohammed Fakhruddin ,  James Karp ,  Kuok-Khian Lo

IPC: G06F17/50 ,  H03K19/003 ,  H05K1/02 ,  H05K3/10

CPC classification number: G06F17/5045 ,  G06F17/5036 ,  G06F17/5054 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19105 ,  H03K19/003

Abstract: A circuit for providing a ground path in an integrated circuit device is described. The circuit comprises a device region formed in a substrate; a substrate tap formed adjacent to the device region; and a conductive path coupled between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias, wherein the conductive path is configured to meet a predetermined design requirement.

Abstract translation: 描述了用于在集成电路器件中提供接地路径的电路。 电路包括形成在衬底中的器件区域; 形成在所述器件区域附近的衬底抽头; 以及通过多个金属层和通孔耦合在所述衬底抽头和接地金属层之间的导电路径，其中所述导电路径被配置为满足预定的设计要求。

公开(公告)号：US11018130B1

公开(公告)日：2021-05-25

申请号：US16573637

申请日：2019-09-17

Applicant: XILINX, INC.

Inventor： Mohammed Fakhruddin

IPC: H01L27/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.

公开(公告)号：US10325901B1

公开(公告)日：2019-06-18

申请号：US15399672

申请日：2017-01-05

Applicant: Xilinx, Inc.

Inventor： Mohammed Fakhruddin ,  James Karp

IPC: H01L27/02 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

Abstract: A circuit for implementing a discharge path in an input/output circuit of an integrated circuit is described. The circuit comprises an input/output pad; a first node coupled to a power reference voltage; a first impedance element implemented between the first node and the input/output pad; a second node coupled to a ground reference voltage; and a second impedance element implemented between the second node and the input/output pad. A method of implementing a discharge path in an input/output circuit of an integrated circuit is also disclosed.

公开(公告)号：US10861848B2

公开(公告)日：2020-12-08

申请号：US16110894

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

IPC: H01L27/06 ,  H01L27/02 ,  H01L49/02 ,  H01L29/73 ,  H01L29/78

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.