公开(公告)号：US10608618B1

公开(公告)日：2020-03-31

申请号：US16022206

申请日：2018-06-28

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  Milind Goel ,  Hari Bilash Dubey

IPC: H03K3/00 ,  H03K3/356 ,  H03K19/017

Abstract: A method, non-transitory computer readable medium, and circuit for wide range voltage translation using monostable multi-vibrator feedback are disclosed. The circuit includes a bias generation segment and a voltage translator to shift a voltage level of a signal from a first voltage domain of a digital system to a second voltage domain of the digital system. The bias generation segment is configured to detect a voltage range of the second voltage domain and to configure the voltage translator responsive to the voltage range. The voltage translator is configured to directly shift the voltage level of the signal to the second voltage domain. The second voltage domain has voltage levels that are higher than a maximum voltage that can be tolerated by transistors in the digital system.

公开(公告)号：US11777489B1

公开(公告)日：2023-10-03

申请号：US17747387

申请日：2022-05-18

Applicant: Xilinx, Inc.

Inventor： Hari Bilash Dubey ,  Milind Goel ,  Venkata Siva Satya Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama Subrahmanyam Lanka

IPC: H03K17/22 ,  H03K17/10 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/223 ,  H03K17/102 ,  H03K19/0013 ,  H03K19/00315

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.

公开(公告)号：US11664800B1

公开(公告)日：2023-05-30

申请号：US16511925

申请日：2019-07-15

Applicant: Xilinx, Inc.

Inventor： VSS Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama S. Lanka ,  Hari Bilash Dubey ,  Milind Goel

IPC: H03K17/687

CPC classification number: H03K17/6872

Abstract: A circuit for implementing an input/output connection in an integrated circuit device is described. The circuit comprises a pull-up circuit comprising a first plurality of transistors coupled in series, wherein a gate of a first transistor of the first plurality of transistors is configured to receive a first dynamic bias signal; a pull-down circuit comprising a second plurality of transistors coupled in series, the pull-down circuit being coupled to the pull-up circuit at an output node, wherein a gate of a first transistor of the second plurality of transistors is configured to receive a second dynamic bias signal; and an input/output contact coupled to the output node. A circuit for implementing an input/output connection in an integrated circuit device including a splitter circuit for receiving an input signal on an input pad is also described. A method of implementing an input/output connection in an integrated circuit device is also described.

公开(公告)号：US11750185B2

公开(公告)日：2023-09-05

申请号：US17482336

申请日：2021-09-22

Applicant: XILINX, INC.

Inventor： Siva Charan Nimmagadda ,  Xiaobao Wang ,  Vinit Shah ,  Sabarathnam Ekambaram ,  Hari Bilash Dubey

IPC: H03K5/156 ,  H03K5/134 ,  H03K5/135 ,  G11C7/22

CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K5/134 ,  H03K5/135

Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

公开(公告)号：US10484041B2

公开(公告)日：2019-11-19

申请号：US15703800

申请日：2017-09-13

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  VSS Prasad Babu Akurathi ,  Milind Goel ,  Hari Bilash Dubey

IPC: H04B1/00 ,  H04B1/58 ,  H04B1/44 ,  H04B1/04 ,  H03K19/0185

Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

公开(公告)号：US20190081656A1

公开(公告)日：2019-03-14

申请号：US15703800

申请日：2017-09-13

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  VSS Prasad Babu Akurathi ,  Milind Goel ,  Hari Bilash Dubey

IPC: H04B1/58 ,  H04B1/04 ,  H04B1/00 ,  H04B1/44

CPC classification number: H04B1/586 ,  H03K19/018521 ,  H04B1/005 ,  H04B1/0475 ,  H04B1/44

Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

公开(公告)号：US09998120B1

公开(公告)日：2018-06-12

申请号：US15448494

申请日：2017-03-02

Applicant: Xilinx, Inc.

Inventor： Sabarathnam Ekambaram ,  Hari Bilash Dubey

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0185 ,  H03K19/177

CPC classification number: H03K19/018521 ,  H03K19/017581 ,  H03K19/1776

Abstract: A circuit for shifting an input common mode voltage is described. The circuit comprises a first current path configured to generate a first current between a reference voltage and a ground potential, the first current path having a first output; a second current path configured to generate a second current between the reference voltage and the ground potential, the second current path having a second output; a first bias current control circuit coupled to the first current path and the second current path, wherein the first bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path; and a second bias current control circuit coupled to the first current path and the second current path, wherein the second bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path. A method of shifting an input common mode voltage is also described.