公开(公告)号：US20240193341A1

公开(公告)日：2024-06-13

申请号：US18078540

申请日：2022-12-09

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Mohit Sharma ,  Chatla Surya Phanindra ,  Sandip Maity ,  Aman Gayasen ,  Srinivasan Dasasathyan

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.

公开(公告)号：US20250077760A1

公开(公告)日：2025-03-06

申请号：US18461992

申请日：2023-09-06

Applicant: Xilinx, Inc.

Inventor： Sandip Maity ,  Chun Zhang ,  Aman Gayasen

IPC: G06F30/398

Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.