公开(公告)号：US11714950B2

公开(公告)日：2023-08-01

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/327 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US20230034736A1

公开(公告)日：2023-02-02

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US20240193341A1

公开(公告)日：2024-06-13

申请号：US18078540

申请日：2022-12-09

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Mohit Sharma ,  Chatla Surya Phanindra ,  Sandip Maity ,  Aman Gayasen ,  Srinivasan Dasasathyan

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.