公开(公告)号：US09166584B1

公开(公告)日：2015-10-20

申请号：US14300146

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Srinivasa L. Karumajji ,  Vikram Santurkar

IPC: H03K19/173 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0013 ,  H03K19/017509 ,  H03K19/017581

Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.

Abstract translation: 公开了一种用于以当前编码格式通信数据信号的装置。 该装置包括第一逻辑块和第二逻辑块。 第一逻辑块包括被配置为提供第一电压编码二进制信号的第一电压模式逻辑（VML）电路和被配置为将电压编码二进制信号转换为电流编码二进制信号的编码器电路。 第二逻辑块包括被配置为从第一逻辑块接收当前编码的二进制信号并将当前编码的二进制信号转换为第二电压编码二进制信号的解码器电路。 由第二电压编码二进制信号编码的逻辑状态等于由第一电压编码二进制信号编码的逻辑状态。 第二逻辑块还包括耦合到解码器电路并被配置为接收和处理第二电压编码二进制信号的第二VML电路。

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。