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    Analog and radio frequency (RF) system-level simulation using frequency relaxation
    1.
    发明申请
    Analog and radio frequency (RF) system-level simulation using frequency relaxation 有权
    使用频率弛豫的模拟和射频（RF）系统级仿真

    公开(公告)号：US20060047491A1

    公开(公告)日：2006-03-02

    申请号：US11208844

    申请日：2005-08-22

    申请人： Xin Li ,  Yang Xu ,  Peng Li ,  Lawrence Pileggi

    发明人： Xin Li ,  Yang Xu ,  Peng Li ,  Lawrence Pileggi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.

    摘要翻译： 模拟和射频系统级仿真使用频率弛豫。 本发明的实施例使用容纳大系统尺寸和复杂信号空间的模拟/ RF系统级仿真的频率松弛方法。 模拟器可以通过将系统划分成块并且模拟通过块的输入信号的传播来确定系统的输出响应。 输入信号可以采取各种形式，包括多音频正弦信号，连续频谱信号和/或随机信号。 应用频率弛豫来产生个体反应。 可以基于获得各个响应的收敛来计算输出响应。 模拟器的实施例的输入可以是电路网表或块级宏模型。

    Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
    2.
    发明授权
    Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations 有权
    定义具有大规模工艺和环境变化的逻辑电路的时序优化的统计灵敏度

    公开(公告)号：US07487486B2

    公开(公告)日：2009-02-03

    申请号：US11629445

    申请日：2005-06-11

    申请人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

    发明人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

    IPC分类号： G06F17/50 ,  G06F7/60 ,  G06F7/52

    CPC分类号： G06F17/5031 ,  G06F2217/10

    摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

    摘要翻译： 目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。 最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。 本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。 定义了路径和弧线的统计灵敏度。 显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。 描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。 提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

    Active resistors for reduction of transient power grid noise
    3.
    发明申请
    Active resistors for reduction of transient power grid noise 审中-公开
    用于减少瞬态电网噪声的有源电阻

    公开(公告)号：US20070019447A1

    公开(公告)日：2007-01-25

    申请号：US11176055

    申请日：2005-07-07

    申请人： Gokce Keskin ,  Xin Li ,  Lawrence Pileggi

    发明人： Gokce Keskin ,  Xin Li ,  Lawrence Pileggi

    IPC分类号： H02H7/10

    CPC分类号： H03K19/00361 ,  H01L27/0288 ,  H03K17/165

    摘要： Active resistors for reduction of transient power grid noise. An active resistance added in parallel to the operating circuit blocks of a semiconductor device. This resistance increases the damping ratio of the power grid, which in turn decreases the number and the magnitude of oscillations and/or noise resulting from step disturbances of the power supply current. The active resistance can implemented by a transistor connected to a bias voltage. Alternatively, the active resistance can be implemented by a drive transistor with a gain stage, or two active resistors where one responds to overshoots in the current flow and the second active resistor responds to droops in the current flow.

    摘要翻译： 用于减少瞬态电网噪声的有源电阻。 与半导体器件的工作电路块并联的有源电阻。 该电阻增加了电力网的阻尼比，而电网的阻尼比又降低了由电源电流的阶跃扰动引起的振荡和/或噪声的数量和幅度。 有源电阻可以由连接到偏置电压的晶体管实现。 或者，有源电阻可以由具有增益级的驱动晶体管或两个有源电阻器来实现，其中一个响应于电流中的过冲而第二有效电阻器响应电流中的下降。

    Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations
    4.
    发明申请
    Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations 有权
    定义具有大规模过程和环境变化的逻辑电路的时序优化的统计灵敏度

    公开(公告)号：US20080072198A1

    公开(公告)日：2008-03-20

    申请号：US11629445

    申请日：2005-06-11

    申请人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

    发明人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/10

    摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

    摘要翻译： 目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。 最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。 本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。 定义了路径和弧线的统计灵敏度。 显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。 描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。 提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

    Optimization and design method for configurable analog circuits and devices
    7.
    发明授权
    Optimization and design method for configurable analog circuits and devices 有权
    可配置模拟电路和器件的优化设计方法

    公开(公告)号：US07350164B2

    公开(公告)日：2008-03-25

    申请号：US10978497

    申请日：2004-11-01

    申请人： Yang Xu ,  Lawrence Pileggi ,  Stephen P. Boyd

    发明人： Yang Xu ,  Lawrence Pileggi ,  Stephen P. Boyd

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  Y02T10/82

    摘要： Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application. In some embodiments, characterization is accomplished by formulating a configurable design problem as an optimization with recourse problem, for example, a geometric programming with recourse (GPR) problem. Devices can be produced for multiple applications from the application domain using the same optimized fabric to provide predictable performance.

    摘要翻译： 可配置的模拟电路和器件的优化设计方法。 给定应用领域的实现架构可以根据设备和寄生效应进行准确的预定义。 定制结构被设计和表征以应用于织物以定制特定应用的设备。 在一些实施例中，通过将可配置设计问题配置为具有追索问题的优化来实现表征，例如具有追索（GPR）问题的几何规划。 可以使用相同的优化结构从应用程序领域为多个应用程序生成设备，以提供可预测的性能。

    Methods, systems, and computer program products for modeling nonlinear systems
    8.
    发明申请
    Methods, systems, and computer program products for modeling nonlinear systems 审中-公开
    用于非线性系统建模的方法，系统和计算机程序产品

    公开(公告)号：US20050021319A1

    公开(公告)日：2005-01-27

    申请号：US10859621

    申请日：2004-06-03

    申请人： Peng Li ,  Lawrence Pileggi

    发明人： Peng Li ,  Lawrence Pileggi

    IPC分类号： G06F17/10 ,  G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/504

    摘要： According to some embodiments of the present invention, a nonlinear system may be modeled by obtaining a transfer function for the nonlinear system and generating a Taylor series expansion of the transfer function. The Taylor series expansion includes a plurality of moments respectively corresponding to a plurality of coefficients of the Taylor series terms. At least one Krylov subspace is derived that matches at least one of the plurality of moments. The nonlinear system is modeled using the at least one Krylov subspace.

    摘要翻译： 根据本发明的一些实施例，可以通过获得非线性系统的传递函数并生成传递函数的泰勒级数展开来建模非线性系统。 泰勒级数展开包括分别对应于泰勒级数项的多个系数的多个力矩。 导出至少一个Krylov子空间，其匹配多个力矩中的至少一个。 非线性系统使用至少一个Krylov子空间建模。

    Optimization and design method for configurable analog circuits and devices
    9.
    发明申请
    Optimization and design method for configurable analog circuits and devices 有权
    可配置模拟电路和器件的优化设计方法

    公开(公告)号：US20050273732A1

    公开(公告)日：2005-12-08

    申请号：US10978497

    申请日：2004-11-01

    申请人： Yang Xu ,  Lawrence Pileggi ,  Stephen Boyd

    发明人： Yang Xu ,  Lawrence Pileggi ,  Stephen Boyd

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  Y02T10/82

    摘要： Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application. In some embodiments, characterization is accomplished by formulating a configurable design problem as an optimization with recourse problem, for example, a geometric programming with recourse (GPR) problem. Devices can be produced for multiple applications from the application domain using the same optimized fabric to provide predictable performance.

    摘要翻译： 可配置的模拟电路和器件的优化设计方法。 给定应用领域的实现架构可以根据设备和寄生效应进行准确的预定义。 定制结构被设计和表征以应用于织物以定制特定应用的设备。 在一些实施例中，通过将可配置设计问题配置为具有追索问题的优化来实现表征，例如具有追索（GPR）问题的几何规划。 可以使用相同的优化结构从应用程序领域为多个应用程序生成设备，以提供可预测的性能。

    Placement method for integrated circuit design using topo-clustering
    10.
    发明授权
    Placement method for integrated circuit design using topo-clustering 有权

    公开(公告)号：US06961916B2

    公开(公告)日：2005-11-01

    申请号：US10136161

    申请日：2002-05-01

    申请人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    发明人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.