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16 条记录 (耗时 0.015 秒)

    Self-driving circuit for a DC/DC converter
    1.
    发明授权
    Self-driving circuit for a DC/DC converter 有权
    用于DC / DC转换器的自驱动电路

    公开(公告)号：US06839246B1

    公开(公告)日：2005-01-04

    申请号：US10169238

    申请日：2000-01-11

    申请人： Xingzhu Zhang ,  Xiaopeng Dong

    发明人： Xingzhu Zhang ,  Xiaopeng Dong

    IPC分类号： H02M3/335

    CPC分类号： H02M3/33592 ,  Y02B70/1475

    摘要： The present invention provides a self-driving circuit of a low voltage, large current, and high power density DC/DC converter. The converter comprises a transformer, power MOS transistors (S), output rectification portion (SRb 1, SR2), filter portion and demagnetizing portion. The first configuration of the self-driving circuit consists of Da, Ra, Ca, Qa for self-driving SR2; and the second configuration consists of Da, Ra, Sa, a delay driving circuit and an isolation differential circuit, for self-driving SR2. The self-driving circuit of the present invention may reduce the cross-conductive loss, and increase the converting efficiency.

    摘要翻译： 本发明提供一种低电压，大电流和高功率密度DC / DC转换器的自驱动电路。 转换器包括变压器，功率MOS晶体管（S），输出整流部分（SRb 1，SR2），滤波器部分和去磁部分。 自驱动电路的第一个配置由自驱动SR2的Da，Ra，Ca，Qa组成; 第二种配置包括用于自驱动SR2的Da，Ra，Sa，延迟驱动电路和隔离差动电路。 本发明的自驱动电路可以减小交叉导电损耗，提高转换效率。

    Self-driving circuit for a DC/DC converter
    2.
    发明授权
    Self-driving circuit for a DC/DC converter 有权
    用于DC / DC转换器的自驱动电路

    公开(公告)号：US06678172B1

    公开(公告)日：2004-01-13

    申请号：US10169239

    申请日：2002-06-26

    申请人： Xingzhu Zhang ,  Xiaopeng Dong

    发明人： Xingzhu Zhang ,  Xiaopeng Dong

    IPC分类号： H02M3335

    CPC分类号： H02M3/338 ,  H02M3/33576

    摘要： The present invention provides a self-driving circuit for DC/DC converter of a low voltage, high current, and high power density. The converter comprises a transformer, output rectification portion SR1 and voltage clamping. The first configuration of the self-driving circuit consists of resisters Ra1, Ra2, capacitors Ca1, Ca2, transistors Qa1, Qa2; and the second configuration consists of Da, small power MOS transistor SRa, an auxiliary winding Nsa, a delay driving circuit and a isolating differential circuit. The self-driving circuit of the present invention may reduce the cross-conductive loss, and increase the converting efficiency.

    摘要翻译： 本发明提供一种用于低压，高电流和高功率密度的DC / DC转换器的自驱动电路。 转换器包括变压器，输出整流部分SR1和电压钳位。 自驱动电路的第一结构由电阻器Ra1，Ra2，电容器Ca1，Ca2，晶体管Qa1，Qa2， 并且第二配置由Da，小功率MOS晶体管SRa，辅助绕组Nsa，延迟驱动电路和隔离差分电路组成。 本发明的自驱动电路可以减小交叉导电损耗，提高转换效率。

    Method and system for implementing timing aware metal fill
    3.
    发明授权
    Method and system for implementing timing aware metal fill 有权
    实现定时感知金属填充的方法和系统

    公开(公告)号：US08161425B1

    公开(公告)日：2012-04-17

    申请号：US11407873

    申请日：2006-04-19

    申请人： David Noice ,  Gary Nunn ,  Inhwan Seo ,  William Kao ,  Xiaopeng Dong

    发明人： David Noice ,  Gary Nunn ,  Inhwan Seo ,  William Kao ,  Xiaopeng Dong

    IPC分类号： G06F17/50

    CPC分类号： H01L23/522 ,  G06F17/5081 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    摘要： An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

    摘要翻译： 公开了一种用于在电气设备上实现金属填充而不引起交叉耦合电容问题的改进方法。 执行定时识别金属填充插入以避免或最小化IC设计上的交叉电容问题。 可以将成本分配给不同的候选金属填充形状。 成本与通过金属填充形状对时序要求的预期影响相关联，成本对应于对时序要求的较低预期影响。 为了满足密度要求，在更高成本的金属填充形状之前插入较低成本的金属填充形状。

    Method and system for implementing metal fill
    4.
    发明授权
    Method and system for implementing metal fill 有权
    实施金属填充的方法和系统

    公开(公告)号：US07661078B1

    公开(公告)日：2010-02-09

    申请号：US11069759

    申请日：2005-02-28

    申请人： David C. Noice ,  William Kao ,  Inhwan Seo ,  Xiaopeng Dong ,  Gary W. Nunn

    发明人： David C. Noice ,  William Kao ,  Inhwan Seo ,  Xiaopeng Dong ,  Gary W. Nunn

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.

    摘要翻译： 公开了用于实现集成电路设计的金属填充物的改进方法和系统。 当实施工程更改订单时，修改布局时，最初将忽略现有的虚拟金属填充几何，即使这导致短路和/或其他DRC违规。 一旦实施了ECO变更，那么由变更与金属填充之间的相互作用引起的违规行为将被修复。

    Method and apparatus for substrate noise analysis using substrate tile model and tile grid
    6.
    发明授权
    Method and apparatus for substrate noise analysis using substrate tile model and tile grid 有权
    使用基板瓦片模型和瓦片网格进行基板噪声分析的方法和装置

    公开(公告)号：US07877713B2

    公开(公告)日：2011-01-25

    申请号：US11769670

    申请日：2007-06-27

    申请人： Vinod Kariat ,  Xiaopeng Dong ,  David Noice

    发明人： Vinod Kariat ,  Xiaopeng Dong ,  David Noice

    IPC分类号： G06F17/50

    CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.

    摘要翻译： 提供了一种用于评估集成电路设计中的衬底噪声传播的方法，所述方法包括：提供指定与所述块的实例相关联的电模型的瓦片定义; 将多个相应的瓦片实例映射到所述基板的相应位置; 获得指示与相应识别的触点相关联的数字切换感应电网波动的各个波形; 以及将电压与由所选择的瓦片实例包围的触点相关联的波形指示衬底噪声注入的瓦片网格的选定瓦片实例相关联。

    STEP UP CONVERTER WITH OVERCURRENT PROTECTION
    9.
    发明申请
    STEP UP CONVERTER WITH OVERCURRENT PROTECTION 审中-公开
    具有过流保护的升压转换器

    公开(公告)号：US20090027928A1

    公开(公告)日：2009-01-29

    申请号：US12180756

    申请日：2008-07-28

    申请人： Xiaopeng Dong ,  Chaojun Zhu

    发明人： Xiaopeng Dong ,  Chaojun Zhu

    IPC分类号： H02H9/02

    CPC分类号： H02J7/0044

    摘要： A step up converter with overcurrent protection is disclosed. The step up converter can precisely limit the output current of the upstream device. Current from the input terminal of the converter is detected and compared with a predetermined maximum current to get a comparison value which is delivered to a close-loop regulator. The overcurrent protection is achieved by the regulator outputting a control signal to fulfill the conduction or resistance increase of a resistive element of the protection circuit. Furthermore, detection of the temperature or the output voltage may trigger shut off of the protection circuit to implement a protection function.

    摘要翻译： 公开了一种具有过电流保护功能的升压转换器。 升压转换器可精确限制上游设备的输出电流。 检测来自转换器的输入端的电流，并将其与预定的最大电流进行比较，以获得递送到闭环调节器的比较值。 过流保护通过调节器输出控制信号来实现，以实现保护电路的电阻元件的导通或电阻增加。 此外，检测温度或输出电压可能触发保护电路的切断以实现保护功能。

    METHOD AND APPARATUS FOR SUBSTRATE NOISE ANALYSIS USING SUBSTRATE TILE MODEL AND TILE GRID
    10.
    发明申请
    METHOD AND APPARATUS FOR SUBSTRATE NOISE ANALYSIS USING SUBSTRATE TILE MODEL AND TILE GRID 有权
    基板噪声分析方法和装置使用基板模型和天线

    公开(公告)号：US20090007032A1

    公开(公告)日：2009-01-01

    申请号：US11769670

    申请日：2007-06-27

    申请人： Vinod KARIAT ,  Xiaopeng Dong ,  David Noice

    发明人： Vinod KARIAT ,  Xiaopeng Dong ,  David Noice

    IPC分类号： G06F17/50

    CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.

    摘要翻译： 提供了一种用于评估集成电路设计中的衬底噪声传播的方法，所述方法包括：提供指定与所述块的实例相关联的电模型的瓦片定义; 将多个相应的瓦片实例映射到所述基板的相应位置; 获得指示与相应识别的触点相关联的数字切换感应电网波动的各个波形; 以及将电压与由所选择的瓦片实例包围的触点相关联的波形指示衬底噪声注入的瓦片网格的选定瓦片实例相关联。