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    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250056911A1

    公开(公告)日：2025-02-13

    申请号：US18751148

    申请日：2024-06-21

    Applicant: Xintec Inc.

    Inventor： Wei-Luen SUEN ,  Chien Wei CHANG ,  Zi-Yu LIAO ,  Jiun-Yen LAI ,  Tsang Yu LIU

    IPC: H01L27/146 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

    Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    2.
    发明公开
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230361144A1

    公开(公告)日：2023-11-09

    申请号：US18304325

    申请日：2023-04-20

    Applicant: Xintec Inc.

    Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang Yu LIU ,  Joey LAI

    IPC: H01L27/146

    CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14623

    Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    3.
    发明公开
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240116751A1

    公开(公告)日：2024-04-11

    申请号：US18480385

    申请日：2023-10-03

    Applicant: Xintec Inc.

    Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG ,  Tsang Yu LIU

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0064 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0118

    Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250081668A1

    公开(公告)日：2025-03-06

    申请号：US18803566

    申请日：2024-08-13

    Applicant: XINTEC INC.

    Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Jiun-Yen LAI ,  Tsang Yu LIU

    IPC: H01L31/02 ,  H01L21/66 ,  H01L31/0216 ,  H01L31/18

    Abstract: A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.

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