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公开(公告)号：US08054673B2
公开(公告)日：2011-11-08
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US20120039113A1
公开(公告)日：2012-02-16
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US20100265749A1
公开(公告)日：2010-10-21
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US08482957B2
公开(公告)日：2013-07-09
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US08098516B2
公开(公告)日：2012-01-17
申请号：US12855896
申请日：2010-08-13
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译： 存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。 每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。 每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。 第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。
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公开(公告)号：US20100080053A1
公开(公告)日：2010-04-01
申请号：US12242331
申请日：2008-09-30
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
IPC分类号： G11C11/02 , G11C11/409
CPC分类号： G11C11/1675 , G11C11/1659
摘要： The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译： 本公开涉及包括以阵列布置的多个磁性隧道结单元的存储器阵列。 每个磁性隧道结单元电连接在位线和源极线之间。 磁性隧道结单元通过使通过磁性隧道结单元的写入电流通过而在高电阻状态和低电阻状态之间切换。 晶体管电连接在磁性隧道结电池和源极线之间。 字线电耦合到晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。
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公开(公告)号：US08068359B2
公开(公告)日：2011-11-29
申请号：US12948838
申请日：2010-11-18
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译： 存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。 每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。 每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。 第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。
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公开(公告)号：US20110063901A1
公开(公告)日：2011-03-17
申请号：US12948838
申请日：2010-11-18
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译： 存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。 每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。 每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。 第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。
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公开(公告)号：US07859891B2
公开(公告)日：2010-12-28
申请号：US12242331
申请日：2008-09-30
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译： 存储器阵列包括以阵列布置的多个磁性隧道结单元。 每个磁性隧道结单元电连接在位线和源极线之间。 磁性隧道结单元通过使通过磁性隧道结单元的写入电流通过而在高电阻状态和低电阻状态之间切换。 字线电耦合到晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。
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公开(公告)号：US20100091546A1
公开(公告)日：2010-04-15
申请号：US12251788
申请日：2008-10-15
申请人： Hongyue Liu , Xuguang Wang , Yong Lu , Yiran Chen
发明人： Hongyue Liu , Xuguang Wang , Yong Lu , Yiran Chen
IPC分类号： G11C17/02 , G11C11/409 , G11C11/02
CPC分类号： G11C17/02 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： One time programmable memory units include a magnetic tunnel junction cell electrically coupled to a bit line and a word line. The magnetic tunnel junction cell is pre-programmed to a first resistance state, and is configured to switch only from the first resistance state to a second resistance state by passing a voltage across the magnetic tunnel junction cell. In some embodiments, a transistor is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. In other embodiments, a device having a rectifying switching characteristic, such as a diode or other non-ohmic device, is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. Methods of pre-programming the one time programmable memory units and reading and writing to the units are also disclosed.
摘要翻译： 一次可编程存储器单元包括电耦合到位线和字线的磁性隧道结单元。 磁性隧道结单元被预编程为第一电阻状态，并且被配置为仅通过使磁性隧道结单元电流通过电压而从第一电阻状态切换到第二电阻状态。 在一些实施例中，晶体管电耦合在磁性隧道结单元与字线或位线之间。 在其他实施例中，具有整流开关特性的器件，例如二极管或其它非欧姆器件，电耦合在磁性隧道结单元与字线或位线之间。 还公开了对一次可编程存储器单元进行预编程以及读取和写入单元的方法。
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