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公开(公告)号：US08054673B2
公开(公告)日：2011-11-08
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US20120039113A1
公开(公告)日：2012-02-16
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US20100265749A1
公开(公告)日：2010-10-21
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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公开(公告)号：US08482957B2
公开(公告)日：2013-07-09
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译： 存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是 在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。
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5.发明授权Predictive thermal preconditioning and timing control for non-volatile memory cells 有权非易失性存储单元的预测性热预处理和时序控制公开(公告)号：US08154914B2
公开(公告)日：2012-04-10
申请号：US13016390
申请日：2011-01-28
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译： 一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。 热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。
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6.发明申请Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权非易失性记忆体的预测热预处理和时序控制公开(公告)号：US20110128778A1
公开(公告)日：2011-06-02
申请号：US13016390
申请日：2011-01-28
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译： 一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。 热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。
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7.发明授权Predictive thermal preconditioning and timing control for non-volatile memory cells 有权非易失性存储单元的预测性热预处理和时序控制公开(公告)号：US07916528B2
公开(公告)日：2011-03-29
申请号：US12414452
申请日：2009-03-30
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译： 一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。 热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。
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公开(公告)号：US07894250B2
公开(公告)日：2011-02-22
申请号：US12405918
申请日：2009-03-17
申请人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
发明人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C11/1697
摘要： A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
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公开(公告)号：US20110019466A1
公开(公告)日：2011-01-27
申请号：US12900303
申请日：2010-10-07
申请人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
发明人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
CPC分类号： G11C29/50 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C11/1697
摘要： A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
摘要翻译： 一种用于修复诸如自旋转矩传递随机存取存储器（STRAM）的非易失性存储单元中的卡入缺陷状况的方法和装置。 在一些实施例中，电阻感测元件具有磁性隧道结（MTJ）和位于电阻感测元件附近的修复平面。 修复平面在MTJ中注入磁场以修复卡住的缺陷状况。
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10.发明申请Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权非易失性记忆体的预测热预处理和时序控制公开(公告)号：US20100246251A1
公开(公告)日：2010-09-30
申请号：US12414452
申请日：2009-03-30
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译： 一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。 热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。
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