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公开(公告)号：US20230363138A1
公开(公告)日：2023-11-09
申请号：US17738661
申请日：2022-05-06
发明人： Yuancheng YANG , Dongxue ZHAO , Tao YANG , Lei LIU , Di WANG , Kun ZHANG , Wenxi ZHOU , Zhiliang XIA , Zongliang HUO
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure comprises a memory cell comprising: a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact coupled to a word line and surrounding a first portion of the insulating layer, and multiple plate line contact segments coupled to multiple plate lines respectively and surrounding a second portion of the insulating layer. The memory structure further comprises a bit line contact coupled to a bit line and coupled to a first end of the cylindrical body, a source line contact coupled to a source line, and a source cap coupled between the source line contact and a second end of the cylindrical body to increase a distance between the source line contact and the plate line contact segments.
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公开(公告)号：US20240215458A1
公开(公告)日：2024-06-27
申请号：US18089838
申请日：2022-12-28
发明人： Yuxuan FANG , Shan LI , Dongxue ZHAO , Lei LIU , Zhiliang XIA
IPC分类号： H10N50/10 , H01L23/528 , H10B61/00 , H10N50/01
CPC分类号： H10N50/10 , H01L23/5283 , H10B61/20 , H10N50/01
摘要： A memory device includes a semiconductor layer and a stack structure over the semiconductor layer. The stack structure includes a cell array region and a staircase structure region. The cell array region includes multiple vertical levels of stacked transistor-magnetic tunnel junction (TMTJ) elements and a plurality of channel structures vertically extending through the stack structure. At least one channel structure includes a vertical core, a vertical magnetic reference layer, and a vertical tunnel barrier layer, which are shared by a set of magnetic tunnel junction (MTJ) elements associated with the at least one channel structure. The set of MTJ elements are located at different vertical levels of the stack structure.
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公开(公告)号：US20230354577A1
公开(公告)日：2023-11-02
申请号：US17731520
申请日：2022-04-28
发明人： Dongxue ZHAO , Tao Yang , Yuancheng Yang , Lei Liu , Di Wang , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and a third gate contact configured to control electrical charge conduction between the first gate contact and the second gate contact. The 3D memory device can utilize dynamic flash memory (DFM), increase storage efficiency, provide tri-gate control, provide different programming options, increase read, program, and erase operation rates, decrease leakage current, increase retention time, and decrease refresh rates.
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公开(公告)号：US20230354599A1
公开(公告)日：2023-11-02
申请号：US17731524
申请日：2022-04-28
发明人： Tao Yang , Dongxue ZHAO , Yuancheng YANG , Lei LIU , Kun ZHANG , Di WANG , Wenxi ZHOU , Zhiliang XIA , Zongliang HUO
IPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/528
CPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/5283
摘要： A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.
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公开(公告)号：US20230354578A1
公开(公告)日：2023-11-02
申请号：US17731523
申请日：2022-04-28
发明人： Di WANG , Lei LIU , Yuancheng YANG , Wenxi ZHOU , Kun ZHANG , Tao YANG , Dongxue ZHAO , Zhiliang XIA , Zongliang HUO
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.
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公开(公告)号：US20240164105A1
公开(公告)日：2024-05-16
申请号：US18090142
申请日：2022-12-28
发明人： Tao YANG , Dongxue ZHAO , Wenxi ZHOU , Zhiliang XIA
CPC分类号： H10B43/35 , G11C16/0483 , H10B41/27 , H10B41/35 , H10B43/27
摘要： A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.
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公开(公告)号：US20240105266A1
公开(公告)日：2024-03-28
申请号：US17950931
申请日：2022-09-22
发明人： Tao YANG , Dongxue ZHAO , Lei LIU , Kun ZHANG , Wenxi ZHOU , Zhiliang XIA , Zongliang HUO
CPC分类号： G11C16/16 , G11C16/0483
摘要： A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.
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