-
公开(公告)号：US20240339402A1
公开(公告)日：2024-10-10
申请号：US18382251
申请日：2023-10-20
发明人： Zhong ZHANG , Kun ZHANG , Wenxi ZHOU , Zhiliang XIA
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC分类号： H01L23/5283 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
摘要： A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.
-
公开(公告)号：US20240282673A1
公开(公告)日：2024-08-22
申请号：US18643322
申请日：2024-04-23
发明人： Linchun WU , Kun ZHANG , Zhong ZHANG , Wenxi ZHOU , Zhiliang XIA
CPC分类号： H01L23/481 , H01L21/4814 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40
摘要： A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.
-
公开(公告)号：US20230354599A1
公开(公告)日：2023-11-02
申请号：US17731524
申请日：2022-04-28
发明人： Tao Yang , Dongxue ZHAO , Yuancheng YANG , Lei LIU , Kun ZHANG , Di WANG , Wenxi ZHOU , Zhiliang XIA , Zongliang HUO
IPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/528
CPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/5283
摘要： A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.
-
公开(公告)号：US20230354578A1
公开(公告)日：2023-11-02
申请号：US17731523
申请日：2022-04-28
发明人： Di WANG , Lei LIU , Yuancheng YANG , Wenxi ZHOU , Kun ZHANG , Tao YANG , Dongxue ZHAO , Zhiliang XIA , Zongliang HUO
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.
-
公开(公告)号：US20230086425A1
公开(公告)日：2023-03-23
申请号：US17993600
申请日：2022-11-23
发明人： Zhongwang SUN , Guangji LI , Kun ZHANG , Ming HU , Jiwei CHENG , Shijin LUO , Kun BAO , Zhiliang XIA
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11529
摘要： Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.
-
公开(公告)号：US20220302149A1
公开(公告)日：2022-09-22
申请号：US17352239
申请日：2021-06-18
发明人： Kun ZHANG , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11556 , H01L27/11582 , H01L27/11524 , H01L27/11526 , H01L27/1157 , H01L27/11573
摘要： Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and stack dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.
-
公开(公告)号：US20190067324A1
公开(公告)日：2019-02-28
申请号：US16047178
申请日：2018-07-27
发明人： Kun ZHANG , Fandong LIU , Zhiliang XIA
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11521 , H01L27/11568 , H01L21/77
CPC分类号： H01L27/11582 , H01L21/77 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157
摘要： Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.
-
公开(公告)号：US20240105266A1
公开(公告)日：2024-03-28
申请号：US17950931
申请日：2022-09-22
发明人： Tao YANG , Dongxue ZHAO , Lei LIU , Kun ZHANG , Wenxi ZHOU , Zhiliang XIA , Zongliang HUO
CPC分类号： G11C16/16 , G11C16/0483
摘要： A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.
-
公开(公告)号：US20230138575A1
公开(公告)日：2023-05-04
申请号：US17539677
申请日：2021-12-01
发明人： Kun ZHANG , Lei LIU , Yuancheng YANG , Wenxi ZHOU , Zhiliang XIA
摘要： Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.
-
公开(公告)号：US20220367510A1
公开(公告)日：2022-11-17
申请号：US17709668
申请日：2022-03-31
发明人： Yaqin LIU , Kun ZHANG , Linchun WU , Wenxi ZHOU
IPC分类号： H01L27/11582 , H01L21/78
摘要： The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming a dielectric stack on a substrate, and forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack. The method also includes forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening. The method further includes removing a portion of the first layer located at the bottom of the first opening from a second side of the dielectric stack to expose a portion of the second layer. The method further includes forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.
-
-
-
-
-
-
-
-
-
搜索结果
36 条记录 (耗时 0.034 秒)
